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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id f9-20020adff989000000b002cea392f000sm29571964wrr.69.2023.03.29.01.55.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 01:55:03 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 29 Mar 2023 10:54:30 +0200 Subject: [PATCH v3 09/17] arm64: dts: mediatek: add mmc support for mt8365-evk MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v3-9-0003e80e0095@baylibre.com> References: <20230203-evk-board-support-v3-0-0003e80e0095@baylibre.com> In-Reply-To: <20230203-evk-board-support-v3-0-0003e80e0095@baylibre.com> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chaotian Jing , Ulf Hansson , Wenbin Mei , Linus Walleij , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, Alexandre Bailon , Fabien Parent , Amjad Ouled-Ameur , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org - Add EMMC support on mmc0 (internal memory) - Add SD-UHS support on mmc1 (external memory) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 138 ++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 2f88562c638a..b5d018686cbe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -97,6 +97,42 @@ &i2c0 { #size-cells = <0>; }; +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x12012>; + vmmc-supply = <&mt6357_vemc_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; + non-removable; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6357_vmch_reg>; + vqmmc-supply = <&mt6357_vio18_reg>; + status = "okay"; +}; + &mt6357_pmic { interrupt-parent = <&pio>; interrupts = <145 IRQ_TYPE_LEVEL_HIGH>; @@ -123,6 +159,108 @@ pins { }; }; + mmc0_default_pins: mmc0-default-pins { + clk-pins { + pinmux = ; + bias-pull-down; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + rst-pins { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + clk-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + ds-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + rst-pins { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + cd-pins { + pinmux = ; + bias-pull-up; + }; + + clk-pins { + pinmux = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + clk-pins { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + cmd-dat-pins { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = ,