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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id f9-20020adff989000000b002cea392f000sm29571964wrr.69.2023.03.29.01.55.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 01:55:06 -0700 (PDT) From: Alexandre Mergnat Date: Wed, 29 Mar 2023 10:54:33 +0200 Subject: [PATCH v3 12/17] arm64: dts: mediatek: add ethernet support for mt8365 SoC MIME-Version: 1.0 Message-Id: <20230203-evk-board-support-v3-12-0003e80e0095@baylibre.com> References: <20230203-evk-board-support-v3-0-0003e80e0095@baylibre.com> In-Reply-To: <20230203-evk-board-support-v3-0-0003e80e0095@baylibre.com> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , AngeloGioacchino Del Regno , Chaotian Jing , Ulf Hansson , Wenbin Mei , Linus Walleij , Zhiyong Tao , =?utf-8?q?Bernhard_Rosenkr=C3=A4nze?= =?utf-8?q?r?= Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, Alexandre Bailon , Fabien Parent , Amjad Ouled-Ameur , Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1363; i=amergnat@baylibre.com; h=from:subject:message-id; bh=7cNEQ8Z3d2N18bBB0ySn0ca/dVK3FcA8H0h1LVefyV8=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkI/zcQ2qKeCqrMP79V92+YPoOhtlDtftApPNzGkg1 h7TrO5aJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZCP83AAKCRArRkmdfjHURV3xEA CSZoyscKEYe7T0Ft3YDPl9VOZdvmX7yZyAEWVJhJzppyb+HSz55wTp/dK6K4/pDgWPFiDbwjBMP2q6 d0kIXSdFnhCj39ysnro6ODeo1eOA5LOdGXmtusno+AxlJV1/UWe9QrRSa8BKEk6vfsIm+E8LbnXl5g 4mVExdV/iF1G6trhPMEC7stxu51G+/R/NtEyQyqUHFYg1ZbAOnnXz0uLsaYO2+FBVWdp/HMAPj4cQo pLFJoN6WOII2P07Q2zxJpTjmUmfnzL/1kvDxLwrbGVORNEQpBEpd5x/HVffMko7QpqQEociMMxu14d X3nznrGUwMMvPIZItAOVJvqDPh9qBRoAMFE6FxcPa7VfJ5zVwdUy7FbkNccmtJbPuJxL6l0Ji4MDss AQMCHekt9oagccrLYS0pspSaaeasktOsm59qcD403dys/j9gMinoHanal4YCtZG6u5ZpMOHFZGYBJF zIsO88urfOIeBY2WGcLLLifHEZwcgUmQoBsggt2iHjhlQiiTMyZ1f+1ubHnMym4KGk+TaG5qPPbAy5 o3yEYKY+4BZEIyofINuqS3JrFWzowGZBgRh5N8dgZILCzIC76qB7h/L+8VqNo03gXXAniUdoMxNL5l cGQJ0WY1xPx89aOQzi+PWAm9KpoZs7L/ffDiRx4HHIVB1/HztjCbKuo2ES0w== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This IP is a 10/100 MAC controller compliant with IEEE 802.3 standards. It supports power management with Energy Efficient Ethernet and Wake-on-LAN specification. Flow control is provided for half-duplex and full-duplex mode. For packet transmission and reception, the controller supports IPv4/UDP/TCP checksum offload and VLAN tag insertion. Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index a67eeca28da5..394a5a61be59 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -438,6 +438,18 @@ mmc2: mmc@11250000 { status = "disabled"; }; + ethernet: ethernet@112a0000 { + compatible = "mediatek,mt8365-eth"; + reg = <0 0x112a0000 0 0x1000>; + mediatek,pericfg = <&infracfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>;