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Tue, 20 Dec 2022 00:02:02 -0800 (PST) Received: from localhost.localdomain ([180.217.146.214]) by smtp.gmail.com with ESMTPSA id u15-20020a65670f000000b00476d1385265sm7559179pgf.25.2022.12.20.00.01.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 00:02:02 -0800 (PST) From: Jim Liu X-Google-Original-From: Jim Liu To: JJLIU0@nuvoton.com, KWLIU@nuvoton.com, jim.t90615@gmail.com, linus.walleij@linaro.org, brgl@bgdev.pl, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org Subject: [PATCH v3 3/3] dt-bindings: gpio: add npcm7xx sgpio driver bindings Date: Tue, 20 Dec 2022 16:01:39 +0800 Message-Id: <20221220080139.1803-4-JJLIU0@nuvoton.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221220080139.1803-1-JJLIU0@nuvoton.com> References: <20221220080139.1803-1-JJLIU0@nuvoton.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add dt-bindings document for the NPCM7xx sgpio driver Signed-off-by: Jim Liu --- Changes for v3: - modify description - modify in/out property name Changes for v2: - modify description --- .../bindings/gpio/nuvoton,sgpio.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml new file mode 100644 index 000000000000..673535314cff --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton SGPIO controller + +maintainers: + - Jim LIU + +description: + This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC. + Nuvoton NPCM7xx SGPIO module is combine serial to parallel IC (HC595) + and parallel to serial IC (HC165), and use APB3 clock to control it. + This interface has 4 pins (D_out , D_in, S_CLK, LDSH). + NPCM7xx/NPCM8xx have two sgpio module each module can support up + to 64 output pins,and up to 64 input pin, the pin is only for gpi or gpo. + GPIO pins have sequential, First half is gpo and second half is gpi. + GPIO pins can be programmed to support the following options + - Support interrupt option for each input port and various interrupt + sensitivity option (level-high, level-low, edge-high, edge-low) + - Directly connected to APB bus and its shift clock is from APB bus clock + divided by a programmable value. + - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines. + nuvoton,input-ngpios GPIO lines is only for gpi. + nuvoton,output-ngpios GPIO lines is only for gpo. + +properties: + compatible: + enum: + - nuvoton,npcm750-sgpio + - nuvoton,npcm845-sgpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + nuvoton,input-ngpios: true + + nuvoton,output-ngpios: true + + bus-frequency: true + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - interrupts + - nuvoton,input-ngpios + - nuvoton,output-ngpios + - clocks + - bus-frequency + +additionalProperties: false + +examples: + - | + #include + #include + gpio8: gpio@101000 { + compatible = "nuvoton,npcm750-sgpio"; + reg = <0x101000 0x200>; + clocks = <&clk NPCM7XX_CLK_APB3>; + interrupts = ; + bus-frequency = <16000000>; + gpio-controller; + #gpio-cells = <2>; + nuvoton,input-ngpios = <64>; + nuvoton,output-ngpios = <64>; + status = "disabled"; + };