From patchwork Mon Dec 19 12:32:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 635864 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36BFCC4167B for ; Mon, 19 Dec 2022 12:33:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232140AbiLSMdD (ORCPT ); Mon, 19 Dec 2022 07:33:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44864 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231531AbiLSMck (ORCPT ); Mon, 19 Dec 2022 07:32:40 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D273F58A; Mon, 19 Dec 2022 04:32:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1671453125; x=1702989125; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=3ata/4PTa5Uu7NYxPIvrTUdKVybjbAKys8AJYQMscqA=; b=nz0fUSjJLf2oEpJJu4afuwa4VbuNqrKl69iJA9t1GwIsPQmGDSwGyZFd pu+YQunbn+HxfUsqo3RfplIwtCCaUe0AtmajGAPVMnxzfXM/4KzYWd3SU uN77E1EqMw/PS3GHEtC6NcvU5miaEezCZKmCWWLo92A6u2XajtRgjly72 Z90pbRjPzC8pQ0owdt4uA8ktKqa2oM6UdmkakZH4rrgfsX50xOrelj6+8 eDxiL8lSJzS5sYEyCfAsE+/ztR0eCGzmDV9GG8xeu7Ljv/aNyEsF/tv88 yT0y4OP1gm8/0qVhBlZpk0L3GAF7EJS/JR9k30+W6YBh0wYrrKD84lSFO g==; X-IronPort-AV: E=McAfee;i="6500,9779,10565"; a="299670701" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="299670701" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Dec 2022 04:32:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10565"; a="896027958" X-IronPort-AV: E=Sophos;i="5.96,255,1665471600"; d="scan'208";a="896027958" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 19 Dec 2022 04:32:03 -0800 Received: by black.fi.intel.com (Postfix, from userid 1003) id CB268F7; Mon, 19 Dec 2022 14:32:33 +0200 (EET) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij Subject: [PATCH v1 1/1] pinctrl: intel: Use same order of bit fields for PADCFG2 Date: Mon, 19 Dec 2022 14:32:29 +0200 Message-Id: <20221219123229.5564-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org PADCFG0 and PADCFG1 are ordered from MSB to LSB, do the same for PADCFG2 bit fields. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-intel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 5e21b0a96efe..9d2791a81ffa 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -88,9 +88,9 @@ #define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0)) #define PADCFG2 0x008 -#define PADCFG2_DEBEN BIT(0) #define PADCFG2_DEBOUNCE_SHIFT 1 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) +#define PADCFG2_DEBEN BIT(0) #define DEBOUNCE_PERIOD_NSEC 31250