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Mon, 31 Oct 2022 10:09:23 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::41c4:5b70:6fec:a963]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::41c4:5b70:6fec:a963%7]) with mapi id 15.20.5746.028; Mon, 31 Oct 2022 10:09:23 +0000 From: Chester Lin To: Rob Herring , Linus Walleij , Krzysztof Kozlowski Cc: Chester Lin , s32@nxp.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Larisa Grigore , Ghennadi Procopciuc , =?utf-8?q?Andreas_F?= =?utf-8?q?=C3=A4rber?= , Matthias Brugger Subject: [PATCH 1/2] dt-bindings: pinctrl: add schema for NXP S32 SoCs Date: Mon, 31 Oct 2022 18:08:42 +0800 Message-Id: <20221031100843.14579-2-clin@suse.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221031100843.14579-1-clin@suse.com> References: <20221031100843.14579-1-clin@suse.com> X-ClientProxiedBy: TYAPR01CA0206.jpnprd01.prod.outlook.com (2603:1096:404:29::26) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|DU2PR04MB8886:EE_ X-MS-Office365-Filtering-Correlation-Id: 9a5f7a76-03ca-41bd-3074-08dabb27fc34 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Larisa Grigore Signed-off-by: Ghennadi Procopciuc Signed-off-by: Chester Lin --- .../pinctrl/nxp,s32cc-siul2-pinctrl.yaml | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml new file mode 100644 index 000000000000..eafb9091cbf7 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32cc-siul2-pinctrl.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2022 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nxp,s32cc-siul2-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32 Common Chassis SIUL2 iomux controller + +maintainers: + - Ghennadi Procopciuc + - Chester Lin + +description: | + Core driver for the pin controller found on S32 Common Chassis SoC. + +properties: + compatible: + enum: + - nxp,s32g-siul2-pinctrl + + reg: + minItems: 5 + maxItems: 6 + description: A list of register regions to be reserved. + + nxp,pins: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + A list of [start, end] pin ID boundaries that correspond to each of + the register regions reserved. + +required: + - compatible + - reg + - nxp,pins + +patternProperties: + '_pins$': + type: object + patternProperties: + '_grp[0-9]$': + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + description: + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + +additionalProperties: false + +examples: + - | + + pinctrl: siul2-pinctrl@4009c240 { + compatible = "nxp,s32g-siul2-pinctrl"; + + /* MSCR range */ + reg = <0x4009c240 0x198>, + <0x44010400 0x2c>, + <0x44010480 0xbc>, + /* MSCR range */ + <0x4009ca40 0x150>, + <0x44010c1c 0x45c>, + <0x440110f8 0x108>; + + /* MSCR range */ + nxp,pins = <0 101>, + <112 122>, + <144 190>, + /* IMCR range */ + <512 595>, + <631 909>, + <942 1007>; + + llce_can0_pins { + llce_can0_grp0 { + pinmux = <0x2b0>; + input-enable; + slew-rate = <0x00>; + }; + + llce_can0_grp1 { + pinmux = <0x2c2>; + output-enable; + slew-rate = <0x00>; + }; + }; + }; +...