Message ID | 20221016170035.35014-32-krzysztof.kozlowski@linaro.org |
---|---|
State | Accepted |
Commit | c535fe66f4a5df69c57faca1fc04a6c1b50240b9 |
Headers | show |
Series | pinctrl/arm64: qcom: continued - fix Qualcomm TLMM pinctrl schema warnings (third set) | expand |
On Sun, 16 Oct 2022 13:00:32 -0400, Krzysztof Kozlowski wrote: > The TLMM pin controller follows generic pin-controller bindings, so > should have subnodes with '-state' and '-pins'. Otherwise the subnodes > (level one and two) are not properly matched. This method also unifies > the bindings with other Qualcomm TLMM and LPASS pinctrl bindings. > > Applied, thanks! [31/34] dt-bindings: pinctrl: qcom,sdx65: fix matching pin config https://git.kernel.org/krzk/linux-dt/c/c535fe66f4a5df69c57faca1fc04a6c1b50240b9 Best regards,
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml index cdfcf29dffee..0f796f1f0104 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdx65-pinctrl.yaml @@ -49,8 +49,10 @@ patternProperties: oneOf: - $ref: "#/$defs/qcom-sdx65-tlmm-state" - patternProperties: - ".*": + "-pins$": $ref: "#/$defs/qcom-sdx65-tlmm-state" + additionalProperties: false + '$defs': qcom-sdx65-tlmm-state: type: object @@ -175,13 +177,13 @@ examples: }; uart-w-subnodes-state { - rx { + rx-pins { pins = "gpio4"; function = "blsp_uart1"; bias-pull-up; }; - tx { + tx-pins { pins = "gpio5"; function = "blsp_uart1"; bias-disable;