From patchwork Tue Mar 15 15:27:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 551503 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCA75C433F5 for ; Tue, 15 Mar 2022 15:27:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349593AbiCOP2g (ORCPT ); Tue, 15 Mar 2022 11:28:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50014 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349590AbiCOP2f (ORCPT ); Tue, 15 Mar 2022 11:28:35 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4639D50B17; Tue, 15 Mar 2022 08:27:23 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.90,183,1643641200"; d="scan'208";a="114498173" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 16 Mar 2022 00:27:22 +0900 Received: from localhost.localdomain (unknown [10.226.92.209]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 2F7FC4008493; Wed, 16 Mar 2022 00:27:20 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring Cc: Biju Das , Geert Uytterhoeven , Lad Prabhakar , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Biju Das Subject: [PATCH 1/2] dt-bindings: pinctrl: renesas: Document RZ/G2UL pinctrl Date: Tue, 15 Mar 2022 15:27:16 +0000 Message-Id: <20220315152717.20045-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document Renesas RZ/G2UL pinctrl bindings. RZ/G2UL GPIO block is almost identical to RZ/G2L and has lesser pins compared to RZ/G2L. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- .../bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 08ea34f39574..71057e570e49 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -11,8 +11,8 @@ maintainers: - Lad Prabhakar description: - The Renesas SoCs of the RZ/{G2L,V2L} series feature a combined Pin and GPIO - controller. + The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and + GPIO controller. Pin multiplexing and GPIO configuration is performed on a per-pin basis. Each port features up to 8 pins, each of them configurable for GPIO function (port mode) or in alternate function mode. @@ -21,6 +21,10 @@ description: properties: compatible: oneOf: + - items: + - enum: + - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} + - items: - enum: - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}