From patchwork Fri Feb 25 05:32:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 545989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E57FC4332F for ; Fri, 25 Feb 2022 05:31:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237538AbiBYFbd (ORCPT ); Fri, 25 Feb 2022 00:31:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237536AbiBYFbc (ORCPT ); Fri, 25 Feb 2022 00:31:32 -0500 Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6523426F4D1 for ; Thu, 24 Feb 2022 21:31:00 -0800 (PST) Received: by mail-ot1-x329.google.com with SMTP id w3-20020a056830060300b005ad10e3becaso2933942oti.3 for ; Thu, 24 Feb 2022 21:31:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HRtPNSZKQI7bpMca2A9QDVsOc/ZETx07EAg1FIwVxRw=; b=ey1AszojHGdk6ElmDks4JQxAmGWpwbsn1snjMYN2uIlr31hNGL9IPcMgzwrhn8e+lM YB/KpoLDA/V5rftxgyFs/Vjl7rwz4rHQLN10i6aNTTfILknRP/XbIrIxCqtDp+PAfPH8 SGWy5Hkdp0T3Wc9aSLsy9P0RLwghUc0AxjQU494QJUpE8Sj86nso6vumTNmWeEgA3aLV 3NDTN1aRlIbbZCLGnP77xZxH7k2m27/4+SuL3rX0EnzCbgOMcKFG+5hG1lAsgiXEDmsH nn37zuCYbkBKl2hnmQ1yVk+8+taasBOaUDPUF31W5oDHJ1F9x0ZleouXOpJ2jXbcPl72 1wPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=HRtPNSZKQI7bpMca2A9QDVsOc/ZETx07EAg1FIwVxRw=; b=r7QfjqrqyTzmGptDXoHYL6rXuvH1mBmGNU0NN7qgC4vLcOT/Kchdrb6M4G12hHzqPQ sTgP7aKQSW6q3Aut+Ly/Vz4g5B1pTnUpTXFMjOG5nMpRPDGgGcfPtqrTtr3QaNf9FJIj 3OO7NGplIEOYptmBque6UCPy8JxDTi2ISR35vqnvPKBf140QoZDa0PwLuP6K2Z/8kS8o tBBILv1dP/CgFQ9myXCe+X9NSUE0kbAVIIivaD7dGSYz+cmNYDvhPYNW524xJy7AJQXz /ypuP8vXOLJpOavFFCCZLgvfb+EZSdWjjBHOxWDI04AbBgOJTiVTAucre9+U2U3W6Dd9 C3lQ== X-Gm-Message-State: AOAM532yPNxOcnvqUIpwhluQPNkdRJk2Wn9NDGAcIJeNexOvQbXDwV7p ffnn7bpCy5hTEf7Jae3sAFmLIA== X-Google-Smtp-Source: ABdhPJx7KHcnf0maHZp12bzMaaJY6bovqf/blb/HwIu60QT2OTlaX5YXyn9G2uSqbkDsjJPVBX8hCA== X-Received: by 2002:a05:6830:b92:b0:5af:44c9:f115 with SMTP id a18-20020a0568300b9200b005af44c9f115mr2265651otv.24.1645767059704; Thu, 24 Feb 2022 21:30:59 -0800 (PST) Received: from ripper.. ([2600:1700:a0:3dc8:205:1bff:fec0:b9b3]) by smtp.gmail.com with ESMTPSA id hj9-20020a056870c90900b000d3d15ecd18sm830823oab.8.2022.02.24.21.30.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Feb 2022 21:30:59 -0800 (PST) From: Bjorn Andersson To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sc8280xp TLMM binding Date: Thu, 24 Feb 2022 21:32:56 -0800 Message-Id: <20220225053257.2479279-1-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Qualcomm SC8280XP platform contains a single block of registers for the TLMM block. This provides pinconf and pinmux for 228 GPIOs, 2 UFS_RESET pins and one SDC interface. Signed-off-by: Bjorn Andersson --- .../pinctrl/qcom,sc8280xp-pinctrl.yaml | 153 ++++++++++++++++++ 1 file changed, 153 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml new file mode 100644 index 000000000000..4199dfe992e0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc8280xp-pinctrl.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SC8280XP TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SC8280XP platform. + +allOf: + - $ref: "pinctrl.yaml#" + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sc8280xp-tlmm + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sc8280xp-tlmm-state" + +'$defs': + qcom-sc8280xp-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-1][0-9]|22[0-7])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset, ufs1_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9, + cmu_rng, cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, + ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, + ddr_pxi6, ddr_pxi7, dp2_hot, dp3_hot, edp0_lcd, edp1_lcd, + edp2_lcd, edp3_lcd, edp_hot, emac0_dll, emac0_mcg0, emac0_mcg1, + emac0_mcg2, emac0_mcg3, emac0_phy, emac0_ptp, emac1_dll0, + emac1_dll1, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, + emac1_phy, emac1_ptp, gcc_gp1, gcc_gp2, gcc_gp3, gcc_gp4, + gcc_gp5, gpio, hs1_mi2s, hs2_mi2s, hs3_mi2s, ibi_i3c, + jitter_bist, lpass_slimbus, mdp0_vsync0, mdp0_vsync1, + mdp0_vsync2, mdp0_vsync3, mdp0_vsync4, mdp0_vsync5, + mdp0_vsync6, mdp0_vsync7, mdp0_vsync8, mdp1_vsync0, + mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4, + mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync, + mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws, mi2s1_data0, + mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0, mi2s2_data1, + mi2s2_sck, mi2s2_ws, mi2s_mclk1, mi2s_mclk2, pcie2a_clkreq, + pcie2b_clkreq, pcie3a_clkreq, pcie3b_clkreq, pcie4_clkreq, + phase_flag, pll_bist, pll_clk, prng_rosc0, prng_rosc1, + prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qspi, qspi_clk, + qspi_cs, qup0, qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, + qup9, qup10, qup11, qup12, qup13, qup14, qup15, qup16, qup17, + qup18, qup19, qup20, qup21, qup22, qup23, rgmii_0, rgmii_1, + sd_write, sdc40, sdc42, sdc43, sdc4_clk, sdc4_cmd, tb_trig, + tgu, tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + usb0_dp, usb0_phy, usb0_sbrx, usb0_sbtx, usb0_usb4, usb1_dp, + usb1_phy, usb1_sbrx, usb1_sbtx, usb1_usb4, usb2phy_ac, + vsense_trigger ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@3100000 { + compatible = "qcom,sc8280x-tlmm"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 230>; + + gpio-wo-subnode-state { + pins = "gpio1"; + function = "gpio"; + }; + + uart-w-subnodes-state { + rx { + pins = "gpio4"; + function = "qup14"; + bias-pull-up; + }; + + tx { + pins = "gpio5"; + function = "qup14"; + bias-disable; + }; + }; + }; +...