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Tue, 1 Feb 2022 14:22:31 -0800 From: Dipen Patel To: , , , , , , , , , , , CC: Dipen Patel Subject: [PATCH v4 07/11] gpio: tegra186: Add HTE in gpio-tegra186 driver Date: Tue, 1 Feb 2022 14:26:26 -0800 Message-ID: <20220201222630.21246-8-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220201222630.21246-1-dipenp@nvidia.com> References: <20220201222630.21246-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: d61fe7cc-6518-4608-f921-08d9e5d157ac X-MS-TrafficTypeDiagnostic: CH2PR12MB4906:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3631; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3Vk+qTWTKKbFWWoR1nXfCCBv+fk1YQilF1Nbw1eabdly7PKvoXMQAkDOUxC8owRpwRK0l8vmQiVpjbIAPN6ZaD0BAinHrhkvjlCGsoc/+OVoD6vXDjBOi+4IMIE2CmYzzlVfoSCSwZ9OlWQWuTL5ycARM+BotHxL3S47s6qcYP0AVrYCkOMDHA/pLw2ITlOWFe7pkIKw+Smy83ei6od2D/9Bs0RzrWY1RTg7vbDUwCEZ61j1yJiJyHrTizFxOFug5ZLwhItEBB/akHjctju/71lQPUINarkt3FAv72WvNaoMB+y5a9liGjF+bR4g6CGZAGv/8RyIFZLwOe+Snve2JR5RfLEZ3/kSATCMiynKkeaG9TYxoJx49nTursZffI26tBn9gIyTadltxqwnH7aX/mxyU6J93TZKNcwPwQLkYXzaxvlZoZkIsfXCrDc8mgR03FNQoUzVTCV9KozMZQdfEQRHHQ/2/87e0kWuDlKlO9lkvM5BRgUNTPah8V1WSYSXlwmMhRIHhft5tH2IWp/kKR8JuRsvApo1KB/KYgzDN16IzXM1pKZsiaEIop3370sQMmEE/7fgFsR+R2Z+7ydpRitiPPlO14AOyy7COAxD4fJQntZbFjFcxqkaXXci/XqAbDJx8CUe4Bw4tXlV5FiXzf+bqAgCdmJYZKgjV6jheZj/mKIWPIcXjHIcFv55Qmo1kp8eeT5LurgPPS77cLnxz9LzNzLSjVPUUb+PAcCKrPTmM5d/bixbklip+3tBy3tTNf0SqavdoCNkp57HvfjEJA== X-Forefront-Antispam-Report: CIP:12.22.5.235; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE; SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(508600001)(81166007)(110136005)(921005)(356005)(86362001)(83380400001)(7416002)(5660300002)(2906002)(82310400004)(7696005)(70586007)(6666004)(70206006)(8936002)(8676002)(36756003)(186003)(4326008)(47076005)(2616005)(336012)(40460700003)(107886003)(316002)(26005)(426003)(36860700001)(1076003)(2101003)(83996005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Feb 2022 22:22:32.9640 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d61fe7cc-6518-4608-f921-08d9e5d157ac X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.235]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT018.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4906 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Tegra194 AON GPIO controller with the use of its internal hardware timestamping engine (HTE) also known as GTE can timestamp GPIO lines through system counter. This patch implements enable/disable callbacks for the GPIO controller. In enable call, it will set timestamp function bit and GPIO line rising/falling edges in the config register. In disable call, it restores the state. Signed-off-by: Dipen Patel --- drivers/gpio/gpio-tegra186.c | 81 +++++++++++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 91c77fccc1e6..3bf6f7e18dcc 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1,8 +1,9 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2017 NVIDIA Corporation + * Copyright (c) 2016-2022 NVIDIA Corporation * * Author: Thierry Reding + * Dipen Patel */ #include @@ -11,6 +12,7 @@ #include #include #include +#include #include #include @@ -35,6 +37,7 @@ #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) +#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7) #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) @@ -75,6 +78,7 @@ struct tegra_gpio_soc { const struct tegra186_pin_range *pin_ranges; unsigned int num_pin_ranges; const char *pinmux; + bool has_gte; }; struct tegra_gpio { @@ -193,6 +197,76 @@ static int tegra186_gpio_direction_output(struct gpio_chip *chip, return 0; } +#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS) + +static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset, + unsigned long flags) +{ + struct tegra_gpio *gpio; + void __iomem *base; + int value; + + if (!gc) + return -EINVAL; + + gpio = gpiochip_get_data(gc); + if (!gpio) + return -ENODEV; + + base = tegra186_gpio_get_base(gpio, offset); + if (WARN_ON(base == NULL)) + return -EINVAL; + + value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); + value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; + + if (flags == HTE_BOTH_EDGES) { + value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; + } else if (flags == HTE_RISING_EDGE_TS) { + value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; + value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; + } else if (flags == HTE_FALLING_EDGE_TS) { + value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; + } + + writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); + + return 0; +} + +static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset, + unsigned long flags) +{ + struct tegra_gpio *gpio; + void __iomem *base; + int value; + + if (!gc) + return -EINVAL; + + gpio = gpiochip_get_data(gc); + if (!gpio) + return -ENODEV; + + base = tegra186_gpio_get_base(gpio, offset); + if (WARN_ON(base == NULL)) + return -EINVAL; + + value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); + value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC; + if (flags == HTE_BOTH_EDGES) { + value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; + } else if (flags == HTE_RISING_EDGE_TS) { + value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; + value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; + } else if (flags == HTE_FALLING_EDGE_TS) { + value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; + } + writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); + + return 0; +} + static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct tegra_gpio *gpio = gpiochip_get_data(chip); @@ -719,6 +793,10 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->gpio.set = tegra186_gpio_set; gpio->gpio.set_config = tegra186_gpio_set_config; gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; + if (gpio->soc->has_gte) { + gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts; + gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts; + } gpio->gpio.base = -1; @@ -971,6 +1049,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .name = "tegra194-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_gte = true, }; #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \