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IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid04.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(70586007)(921005)(70206006)(1076003)(8936002)(86362001)(186003)(82310400004)(6666004)(110136005)(356005)(8676002)(508600001)(4326008)(426003)(2616005)(336012)(36756003)(107886003)(2906002)(36860700001)(47076005)(316002)(5660300002)(7636003)(7696005)(7416002)(26005)(2101003)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Nov 2021 19:29:20.7353 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: abd2939b-f288-4f30-24ac-08d9aeb78c77 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.35]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT034.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4110 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some GPIO controllers can timestamp GPIO lines in real time using hardware timestamp engine. The optional property is added to facilitate this feature. The nvidia GPIO controller has hardware timestamp engine as a backend to timestamp its GPIO lines in a real time. This change set adds hardware-timestamp-engine property to reflect that fact. Signed-off-by: Dipen Patel --- Documentation/devicetree/bindings/gpio/gpio.txt | 8 ++++++++ .../devicetree/bindings/gpio/nvidia,tegra186-gpio.txt | 7 +++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index a8895d339bfe..c6ae2eaf5762 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -167,6 +167,13 @@ left to right from the passed array. An incomplete array (where the number of passed named are less than ngpios) will still be used up until the last provided valid line index. +Optionally, a GPIO controller may have a "hardware-timestamp-engine" property. +This specifies the timestamp engine node. The property is only useful if the +hardware timestamp engine (HTE) serves as a back-end to support hardware +timestamp GPIO lines in a real time and GPIO controller has dependency on the +engine. It will be up to GPIO controller and HTE provider drivers to figure out +the mapping between GPIO controller and HTE namespaces of a given GPIO line. + Example: gpio-controller@00000000 { @@ -180,6 +187,7 @@ gpio-controller@00000000 { "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", "Row A", "Row B", "Row C", "Row D", "NMI button", "poweroff", "reset"; + hardware-timestamp-engine = <&hadrware_ts_engine_node>; } The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt index adff16c71d21..20f6c9e69839 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt @@ -127,6 +127,12 @@ Required properties: - 8: Active low level-sensitive. Valid combinations are 1, 2, 3, 4, 8. +Optional properties: +- hardware-timestamp-engine + AON GPIO controller has timestamp engine which can hardware timestamp + GPIO configured as input and IRQ. This property specifies hardware + timestamp engine (HTE) device-tree node. + Example: #include @@ -162,4 +168,5 @@ gpio@c2f0000 { #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + hardware-timestamp-engine = <&tegra_hte_aon>; };