From patchwork Wed Jun 2 12:03:25 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?J=2E_Neusch=C3=A4fer?= X-Patchwork-Id: 452813 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88286C4708F for ; Wed, 2 Jun 2021 12:04:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72F70613D2 for ; Wed, 2 Jun 2021 12:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229791AbhFBMF4 (ORCPT ); Wed, 2 Jun 2021 08:05:56 -0400 Received: from mout.gmx.net ([212.227.15.19]:55387 "EHLO mout.gmx.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbhFBMFz (ORCPT ); Wed, 2 Jun 2021 08:05:55 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1622635447; bh=2ut7fjvCRXp1vUUCh5jcJNV1bWQfWdPByri+EnaApG4=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=XEpTcTJKIpUmN+jRuMfsthO1SugHY9sL+kIJZWtp+JUGmd5BVuB9nqyW9WzrGlKzB jiruRmE73d3tzDqcA68xNJ6S2GSuqrzIFzJcArEYPnKV3/CvbNnChW7guzOSLJlciQ pV+nHz+yVNqQqFaEG9QMWLylQNf8BKOfoF0n38ME= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from longitude ([37.201.214.247]) by mail.gmx.net (mrgmx004 [212.227.17.190]) with ESMTPSA (Nemesis) id 1M5fIW-1lleRh0AGI-007Eso; Wed, 02 Jun 2021 14:04:07 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Cc: Linus Walleij , Rob Herring , openbmc@lists.ozlabs.org, Tomer Maimon , Joel Stanley , linux-kernel@vger.kernel.org, =?utf-8?q?Jonathan_Neusch=C3=A4fer?= Subject: [PATCH 4/8] dt-bindings: pinctrl: Add Nuvoton WPCM450 Date: Wed, 2 Jun 2021 14:03:25 +0200 Message-Id: <20210602120329.2444672-5-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210602120329.2444672-1-j.neuschaefer@gmx.net> References: <20210602120329.2444672-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:E6+ZEj70X9yV7fiuKCDzxr1LhJdKjksAzp/xm8VL+BUlNTseNAy okeguoiss3CzSzhZbxUI/g8cehAHeD7BYclX1esdvc/7SzljFeMilw82uESa2irNjwShC6Q +ga7VcY3dY3MetH3iuAhMK8bWENWkzICY+Gglqp5UWPQ1qs5H/lemP4T9TStx+g0Oqy9QPw WhabaSlPxi7wEN+qX+qbw== X-UI-Out-Filterresults: notjunk:1; V03:K0:l4v+Hockw6I=:sOCxMcqqcQryI1ft9be5w1 JYsHx3jlluDR2PiCP7kBlHApH55MTdTHpTgE/+5RrRTb6JVeSL+Jp4pfRzlc7w8IJ1xj1KqGc RyKzrHax0LTh5qyf5qaM9fmwbjk0J1oO1ZnoZO8BdULLZYnZUte6RkifQtos1+qThbpzLpn7e UIQqUiIFRi+QqRUOeRsNuBqKgmZRtDNleM8P9KriRfsdsOJN+BWA0GFvUjdIASn9EAAWvtmjS FauoUBzK1Wh0Y85GC/4uLg7QonpojwChodBI5wW7XzKwMxhj7j5hV3vIoebP8H+S5BL0PzIcP 4lMJO0Lr+XlUGrAiCkjNl4odHDweti/2B56O9T3WV8klgPuaCfc+Q+HCePVKeIREQy7AA6WyX NeA5iTyVYcBcsZ+yRVtd9ZDVIAf5P4MRrxF+dc2bQwRfUNhtef9eDmH44HNid9jNkFE39XWyM 7aJybtk2rc3y/TceTbOIWUHriypazDKwZKP1zigqsguajAzzTGJyM68luKZ9PNXlXHHzfY2Gl sB37k7bMm6RidcaeqyE5IuGvX30ZRs/visWcYp6djR9Ukc5Nltdgn5ToHsihRXZIWZz0PV+zP GhBvTxpwIoQlM18YczB5ZUNsnKGYVqH231qfT/hEsvAGfeuZWd+nhK3cvK0QVvu7BQbjwXcSs MDfMhPSkDaHUzIip+1q5vk/krtu9j32+0rwjkvrL4IagrzcVf7bBYf396cJxZsi2c26sRdbAK Tl6x33itHEJuwNW4iyfwLxrvTaGWUWnzadcwnW7WIsG5IxWqzBn/rLMzrcPM84Xnicb1ZoTJq pxZJ9+2N/bNjxCT8qOvJJMgREOFfCHE+3mffre+XfPnc33wA0yphDsu0pMgFOtuDZlRDFHL6l B+kTUiwfU2pfIaFRn2CUPx6883svpHQxJKoAXLKC6ggyefvjZKw+2UipuppqASeUW0wtYBMOk d5Z8HPxwh0jTQjD6/VHOxEYvHHy4mAkdqKudExmYssz4JjhPIFYtg/k0+trb34FofblfbQWdx mE9wNCNMa3h37GjVSTh1lKdxr5/9lkciOMcq7PYBRwa/0DFDc4siZAfPr5WEfwWDq8Oo0Sl3Z Yh/OnC9cU5KIiBsTASd8G/0i0cLNXwf0t31bYGp9H1ygXMX+TSaGBFKRw== Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This binding is heavily based on the one for NPCM7xx, because the hardware is similar. One notable difference is that there are no sub-nodes for GPIO banks, because the GPIO registers are arranged differently. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer --- .../pinctrl/nuvoton,wpcm450-pinctrl.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml -- 2.30.2 diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml new file mode 100644 index 0000000000000..0664fe2b90db6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,wpcm450-pinctrl.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 pin control and GPIO + +maintainers: + - Jonathan Neuschäfer + +properties: + compatible: + const: "nuvoton,wpcm450-pinctrl" + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts: true + +patternProperties: + # There are two kinds of subnodes: + # 1. a pinmux node configures pin muxing for a group of pins (e.g. rmii2) + # 2. a pinctrl node configures properties of a single pin + "^.*$": + if: + type: object + then: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + groups: + description: + One or more groups of pins to mux to a certain function + minItems: 1 + items: + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo, + clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0, + fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11, + fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ] + function: + description: + The function that a group of pins is muxed to + enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp, + hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0, + dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc, + gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4, + fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15, + pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1, + hg2, hg3, hg4, hg5, hg6, hg7 ] + + pins: + description: + A list of pins to configure in certain ways, such as enabling + debouncing + minItems: 1 + items: + enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, + gpio8, gpio9, gpio10, gpio11, gpio12, gpio13, gpio14, + gpio15, gpio16, gpio17, gpio18, gpio19, gpio20, gpio21, + gpio22, gpio23, gpio24, gpio25, gpio26, gpio27, gpio28, + gpio29, gpio30, gpio31, gpio32, gpio33, gpio34, gpio35, + gpio36, gpio37, gpio38, gpio39, gpio40, gpio41, gpio42, + gpio43, gpio44, gpio45, gpio46, gpio47, gpio48, gpio49, + gpio50, gpio51, gpio52, gpio53, gpio54, gpio55, gpio56, + gpio57, gpio58, gpio59, gpio60, gpio61, gpio62, gpio63, + gpio64, gpio65, gpio66, gpio67, gpio68, gpio69, gpio70, + gpio71, gpio72, gpio73, gpio74, gpio75, gpio76, gpio77, + gpio78, gpio79, gpio80, gpio81, gpio82, gpio83, gpio84, + gpio85, gpio86, gpio87, gpio88, gpio89, gpio90, gpio91, + gpio92, gpio93, gpio94, gpio95, gpio96, gpio97, gpio98, + gpio99, gpio100, gpio101, gpio102, gpio103, gpio104, + gpio105, gpio106, gpio107, gpio108, gpio109, gpio110, + gpio111, gpio112, gpio113, gpio114, gpio115, gpio116, + gpio117, gpio118, gpio119, gpio120, gpio121, gpio122, + gpio123, gpio124, gpio125, gpio126, gpio127 ] + + input-debounce: true + phandle: true + + dependencies: + groups: [ function ] + function: [ groups ] + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + #include + #include + pinctrl: pinctrl@b8003000 { + compatible = "nuvoton,wpcm450-pinctrl"; + reg = <0xb8003000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH + 3 IRQ_TYPE_LEVEL_HIGH + 4 IRQ_TYPE_LEVEL_HIGH + 5 IRQ_TYPE_LEVEL_HIGH>; + rmii2 { + groups = "rmii2"; + function = "rmii2"; + }; + + pinctrl_uid: uid { + pins = "gpio14"; + input-debounce = <1>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uid>; + + uid { + label = "UID"; + linux,code = <102>; + gpios = <&pinctrl 14 GPIO_ACTIVE_HIGH>; + }; + };