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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 18sm376829oir.4.2021.03.11.19.41.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Mar 2021 19:41:14 -0800 (PST) From: Bjorn Andersson To: Andy Gross , Bjorn Andersson Cc: Linus Walleij , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Vinod Koul Subject: [PATCH 2/2] arm64: dts: qcom: sm8350: Add wakeup-parent to tlmm Date: Thu, 11 Mar 2021 19:42:18 -0800 Message-Id: <20210312034218.3324410-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20210312034218.3324410-1-bjorn.andersson@linaro.org> References: <20210312034218.3324410-1-bjorn.andersson@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Now that TLMM has the wakeup table, specify the Power Domain Controller to be the wakeup-parent of TLMM. Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 1 + 1 file changed, 1 insertion(+) -- 2.29.2 Reviewed-by: Vinod Koul diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 2c02f451379b..d6295212acf7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -642,6 +642,7 @@ tlmm: pinctrl@f100000 { interrupt-controller; #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 203>; + wakeup-parent = <&pdc>; qup_uart3_default_state: qup-uart3-default-state { rx {