From patchwork Wed Mar 10 12:55:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= X-Patchwork-Id: 397016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7DF63C15511 for ; Wed, 10 Mar 2021 12:56:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4D74264FEF for ; Wed, 10 Mar 2021 12:56:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232830AbhCJMzj (ORCPT ); Wed, 10 Mar 2021 07:55:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39480 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232677AbhCJMzS (ORCPT ); Wed, 10 Mar 2021 07:55:18 -0500 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C803C061760; Wed, 10 Mar 2021 04:55:18 -0800 (PST) Received: by mail-wr1-x431.google.com with SMTP id a18so23176301wrc.13; Wed, 10 Mar 2021 04:55:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h/AGwHU9XsQRptOLIWDEGv4WU7FUVqnsl1GkfkR/WC8=; b=jdyeBKsx7Jrty6lvRE6Zbm3/6opy6rs1HyI/DwFbHGLgeY/+/JmzX3P0r+LGn8x3Nx kSTMFYjA8eG4kq6rj2VKrLQSxtJle7xMadzEuzPApwTk9VFpDf/d5K/4B3Bx7CC0x2mN oKFy/zdY/OvqYBt2GwlSWGjjbp+JcM65/UGr3VNnx7iPa9xgpocWAjqoQllnzfR6jysw WfTIcr8JPHjY28lERXIz74N4lc7BCRBN/E2ugUxKQzN1LF+7vy7tMD0iRI9g/XaZP4Dy APhSl7kElqOIn9nBelDmWkPhfV7L/w0gdcRwKQm6Mq5m+/gWQkGLDFuqn7NygpvqB53Z caWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h/AGwHU9XsQRptOLIWDEGv4WU7FUVqnsl1GkfkR/WC8=; b=QbnF3MLrta0t350+XBm37qPZB4Cnb+xe+VgATrosDrSwGOM5y1VqMsB4njL6ooxGk0 x9VvQi7pQDwlxje3WCuFW6qLqW4NuF19ZgXCxJCPG1c40lT1bmouZdV28rzFRllRcksh xNcfDxn/YnUvERe26335cJJI0wvDuNG+funxo4zAGjawTs455zKI4KMDmEeElylSByef NEonDibi/NA0jMNzJJYfJIoyk9ecmsfBP8glG8ytPSze/aGW3Flh9n2BMVFaj19yWF5B dLwug8DUwUcIz2OsOjIHov7pEPkNL/De50v/+t85MGF9eDGSk3SzR8k+JxG+qwUu+P+s As6A== X-Gm-Message-State: AOAM533EXHXSLHYXLrdigasEa9Ju427jslpfL0a6+rYIhHjeQfch0UAE mnBcJOB7IrvhlpJKrjCjIas= X-Google-Smtp-Source: ABdhPJyumKbRoWOem538X6iRrDgjmK9NeDQp5Hm/uhaOFjWbBIqoQupL2K8ER90pc4FGqkF2M9Lvfg== X-Received: by 2002:a5d:56d0:: with SMTP id m16mr3364620wrw.355.1615380916935; Wed, 10 Mar 2021 04:55:16 -0800 (PST) Received: from skynet.lan ([80.31.204.166]) by smtp.gmail.com with ESMTPSA id v6sm29403398wrx.32.2021.03.10.04.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Mar 2021 04:55:16 -0800 (PST) From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= To: Linus Walleij , Rob Herring , Michael Walle , Bartosz Golaszewski , Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, Jonas Gorski , =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= , Necip Fazil Yildiran , Andy Shevchenko , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v6 12/15] dt-bindings: add BCM63268 pincontroller binding documentation Date: Wed, 10 Mar 2021 13:55:00 +0100 Message-Id: <20210310125504.31886-13-noltari@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210310125504.31886-1-noltari@gmail.com> References: <20210310125504.31886-1-noltari@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add binding documentation for the pincontrol core found in the BCM63268 family SoCs. Signed-off-by: Jonas Gorski Co-developed-by: Jonas Gorski Signed-off-by: Álvaro Fernández Rojas --- v6: add changes suggested by Rob Herring v5: change Documentation to dt-bindings in commit title v4: no changes v3: add new gpio node v2: remove interrupts .../pinctrl/brcm,bcm63268-pinctrl.yaml | 211 ++++++++++++++++++ 1 file changed, 211 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml new file mode 100644 index 000000000000..9ff91ea96aef --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml @@ -0,0 +1,211 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM63268 pin controller + +maintainers: + - Álvaro Fernández Rojas + - Jonas Gorski + +description: |+ + The pin controller node should be the child of a syscon node. + + Refer to the the bindings described in + Documentation/devicetree/bindings/mfd/syscon.yaml + +properties: + compatible: + const: brcm,bcm63268-pinctrl + + gpio: + type: object + properties: + compatible: + const: brcm,bcm63268-gpio + + data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset in the register map for the data register (in bytes). + + dirout: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Offset in the register map for the dirout register (in bytes). + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - gpio-ranges + - '#gpio-cells' + + additionalProperties: false + +patternProperties: + '^.*-pins$': + if: + type: object + then: + properties: + function: + $ref: "pinmux-node.yaml#/properties/function" + enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5, + hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi, + vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data, + nand, gpio35_alt, dectpd, vdsl_phy_override_0, + vdsl_phy_override_1, vdsl_phy_override_2, + vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ] + + pins: + $ref: "pinmux-node.yaml#/properties/pins" + enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19, + gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35 + dectpd_grp, vdsl_phy_override_0_grp, + vdsl_phy_override_1_grp, vdsl_phy_override_2_grp, + vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ] + +required: + - compatible + - gpio + +additionalProperties: false + +examples: + - | + gpio_cntl@100000c0 { + compatible = "brcm,bcm63268-gpio-controller", "syscon", "simple-mfd"; + reg = <0x100000c0 0x80>; + + pinctrl: pinctrl { + compatible = "brcm,bcm63268-pinctrl"; + + gpio { + compatible = "brcm,bcm63268-gpio"; + data = <0xc>; + dirout = <0x4>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 0 52>; + #gpio-cells = <2>; + }; + + pinctrl_serial_led: serial_led-pins { + pinctrl_serial_led_clk: serial_led_clk-pins { + function = "serial_led_clk"; + pins = "gpio0"; + }; + + pinctrl_serial_led_data: serial_led_data-pins { + function = "serial_led_data"; + pins = "gpio1"; + }; + }; + + pinctrl_hsspi_cs4: hsspi_cs4-pins { + function = "hsspi_cs4"; + pins = "gpio16"; + }; + + pinctrl_hsspi_cs5: hsspi_cs5-pins { + function = "hsspi_cs5"; + pins = "gpio17"; + }; + + pinctrl_hsspi_cs6: hsspi_cs6-pins { + function = "hsspi_cs6"; + pins = "gpio8"; + }; + + pinctrl_hsspi_cs7: hsspi_cs7-pins { + function = "hsspi_cs7"; + pins = "gpio9"; + }; + + pinctrl_adsl_spi: adsl_spi-pins { + pinctrl_adsl_spi_miso: adsl_spi_miso-pins { + function = "adsl_spi_miso"; + pins = "gpio18"; + }; + + pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins { + function = "adsl_spi_mosi"; + pins = "gpio19"; + }; + }; + + pinctrl_vreq_clk: vreq_clk-pins { + function = "vreq_clk"; + pins = "gpio22"; + }; + + pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins { + function = "pcie_clkreq_b"; + pins = "gpio23"; + }; + + pinctrl_robosw_led_clk: robosw_led_clk-pins { + function = "robosw_led_clk"; + pins = "gpio30"; + }; + + pinctrl_robosw_led_data: robosw_led_data-pins { + function = "robosw_led_data"; + pins = "gpio31"; + }; + + pinctrl_nand: nand-pins { + function = "nand"; + group = "nand_grp"; + }; + + pinctrl_gpio35_alt: gpio35_alt-pins { + function = "gpio35_alt"; + pin = "gpio35"; + }; + + pinctrl_dectpd: dectpd-pins { + function = "dectpd"; + group = "dectpd_grp"; + }; + + pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins { + function = "vdsl_phy_override_0"; + group = "vdsl_phy_override_0_grp"; + }; + + pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins { + function = "vdsl_phy_override_1"; + group = "vdsl_phy_override_1_grp"; + }; + + pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins { + function = "vdsl_phy_override_2"; + group = "vdsl_phy_override_2_grp"; + }; + + pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins { + function = "vdsl_phy_override_3"; + group = "vdsl_phy_override_3_grp"; + }; + + pinctrl_dsl_gpio8: dsl_gpio8-pins { + function = "dsl_gpio8"; + group = "dsl_gpio8"; + }; + + pinctrl_dsl_gpio9: dsl_gpio9-pins { + function = "dsl_gpio9"; + group = "dsl_gpio9"; + }; + }; + };