From patchwork Thu Dec 3 07:08:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 336926 Delivered-To: patch@linaro.org Received: by 2002:a92:5e16:0:0:0:0:0 with SMTP id s22csp72280ilb; Wed, 2 Dec 2020 23:10:25 -0800 (PST) X-Google-Smtp-Source: ABdhPJwiq2JdaS69l1vB9vJMza3rKHuJrNA7O8nAmRkPatJR7l2CbD3rIzUr3qXHc47Yy5JyEKlM X-Received: by 2002:a17:906:94ca:: with SMTP id d10mr1256837ejy.62.1606979424956; Wed, 02 Dec 2020 23:10:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1606979424; cv=none; d=google.com; s=arc-20160816; b=LTWsi84Wy8Kb6h4uAeU436P55mZeS7aOxM6O2Wdo5oFOqdcKT1mYuNJxwSZgkjAreJ zRBpfqYSTAXVXg6KAC7eHbbvjTziCnWRJfX7xlVJPZCxcfkO+I7dKoQH6Va6luTkzh4B jCmtqsrgFtV/qm0y5w8go9lF+nOqq8iMADfEIzOFHQTckIZkBsxWSziP0c1WgSotl+wq 0mIRVcLtv1AQJc0L2i0+kPhrOzm5hK1xdidsscqD4Lcqe7BX52Ow4opBWFxotYbdRr1u uv9SIlkWrK1mFzKgEYsaqb54ZOE5HWfO2vdOnp0GE4u59yqmhh48vNxRqDcPfg37uaGM 2dnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=cPIaCupkOpFqK9TEMUmTZXrJrKn8gEIynrNdwZYShKI=; b=RenZR9JFO9AItuMzWgCxJH8J/sEGK2VxvK+AXklOfziUVisH+sZO/GHA5xesf3rXhE 711gWJarH0mVFN1H437U5S4TeFfBXRKodJ+HKe6g6Nf5kZ0ln7W8531wS7AlrNbnDAhY JkNXSGeQkD68k3LYBg8bDq3/Gk8ztUqWIntjQLZCGqnfWGTkU9cMtRPgQW8JUlLYdgos bVVrOFyOx377YC2lzeLp70eQgk5WITrjgX2H+BZzCbJWDzdsyt4evOj7stpg2M/LvThp 4/PNTngdJrCTRZtuqET5ypzAlAdo829iFpFZDxKGmOlcjJccG+mNeDGj3r51/S4zYVFN m7Gw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id cf16si625114ejb.135.2020.12.02.23.10.24; Wed, 02 Dec 2020 23:10:24 -0800 (PST) Received-SPF: pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-gpio-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728669AbgLCHKF (ORCPT + 3 others); Thu, 3 Dec 2020 02:10:05 -0500 Received: from mail.kernel.org ([198.145.29.99]:56062 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728574AbgLCHKF (ORCPT ); Thu, 3 Dec 2020 02:10:05 -0500 From: Vinod Koul Authentication-Results: mail.kernel.org; dkim=permerror (bad message/signature format) To: Linus Walleij Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add SM8350 pinctrl bindings Date: Thu, 3 Dec 2020 12:38:59 +0530 Message-Id: <20201203070900.2651127-1-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add device tree binding Documentation details for Qualcomm SM8350 pinctrl driver. Signed-off-by: Vinod Koul --- .../pinctrl/qcom,sdm8350-pinctrl.yaml | 151 ++++++++++++++++++ 1 file changed, 151 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sdm8350-pinctrl.yaml -- 2.26.2 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm8350-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm8350-pinctrl.yaml new file mode 100644 index 000000000000..a47d120a3fd0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm8350-pinctrl.yaml @@ -0,0 +1,151 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm8350-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8350 TLMM block + +maintainers: + - Vinod Koul + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SM8350 platform. + +properties: + compatible: + const: qcom,sm8350-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async, + cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, + mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, + mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12, + mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6, + mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator, + pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, + qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request, + qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0, + qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, + qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, + qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, + qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, + sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, + uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present, + uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ] + + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@f000000 { + compatible = "qcom,sm8350-pinctrl"; + reg = <0x0f100000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 203>; + serial-pins { + pins = "gpio18", "gpio19"; + function = "qup3"; + drive-strength = <8>; + bias-disable; + }; + }; + +...