From patchwork Wed Dec 2 03:24:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Le Moal X-Patchwork-Id: 337246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 184DBC8300F for ; Wed, 2 Dec 2020 03:27:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C5D00221E9 for ; Wed, 2 Dec 2020 03:27:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728192AbgLBD1e (ORCPT ); Tue, 1 Dec 2020 22:27:34 -0500 Received: from esa6.hgst.iphmx.com ([216.71.154.45]:25485 "EHLO esa6.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728185AbgLBD1e (ORCPT ); Tue, 1 Dec 2020 22:27:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1606879653; x=1638415653; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=S1YmWmqvdIYXxQKwYnEAtpW95Vpx9w6kjXteMcQR5RY=; b=ZuSEAoG7swPeG+yqDEt0XayK7tJFr79s0C+2W3LPD4wpn3+BD9zX/tmq CX6Ci7KmLlMGMtBOqECY+k0OdfBpWSvKP5wq2bSXVSgFY6DVydFoCnZpW yrXo9flRLDWNleytAC4tSFR32nl3ZfLYWGp9sIHtJ2haEEunwjv0pvZiD MGVvD6zYfJr8WWGJnmnY6mEDu1ZFliSgJ7CCpXwHTnoXC8/fI6l46V6ZB n0ch5N9zVhVGMTDruuKmDC9Z73yt2W4CCP8iTGQwp71YZ/KmZXsaOPkxW 6CltBt+lCz8y2ndKrPAX3j1gABKs8Jv2S1p9XqcKb5PVY4LMSsSeRf5aW Q==; IronPort-SDR: u7Te5vUvWaHteQ4v9X2uM3FuAnyLjT7xBaT22/U2WjpOqSF6PEu1RxC/J1vAZSF+nIyMUVfcSi pgI/myW4hkhtMsXldhesB8YF8jYNVmTQbHMnJElweG2NOiKqo4Aa1lz+AGXiPvghpSIXYnvEPv TBi9LFkARljWooHisU4K97epykqvqNJfnlULmWmYtJwrMYUd02QKWbTM6VQ5zm8jdtWCD0CqNW TuSacRrlRNzQgoRjO9eSW6iArrvU6Iyotp5BHt8RYRnp0kx0bgdX7UqIYFiJjYTDTyiNgfOvFZ +t8= X-IronPort-AV: E=Sophos;i="5.78,385,1599494400"; d="scan'208";a="155183548" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 02 Dec 2020 11:25:22 +0800 IronPort-SDR: G8x9GZylxyzdBjE+m7q3eVARQmPCipSMMgjLrc2PJZn04fzm1Kj4m29P8hbsYwWzzkNP30NQ+B 5fllgHZuBDn386oIJawl9Y2z2X+b6r/mM= Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Dec 2020 19:10:56 -0800 IronPort-SDR: ULjmesI9CfOWXnL2WIzk01Yw1oMDsd+6stHfW3vf2BM/fVoaTPrBf4K8QsIZZ1WfS8yyjmFqDw brC+uhLeoiyw== WDCIronportException: Internal Received: from phd004834.ad.shared (HELO twashi.fujisawa.hgst.com) ([10.84.71.196]) by uls-op-cesaip02.wdc.com with ESMTP; 01 Dec 2020 19:25:19 -0800 From: Damien Le Moal To: Palmer Dabbelt , linux-riscv@lists.infradead.org, Rob Herring , devicetree@vger.kernel.org, Stephen Boyd , linux-clk@vger.kernel.org, Linus Walleij , linux-gpio@vger.kernel.org, Philipp Zabel Cc: Sean Anderson Subject: [PATCH v4 08/21] dt-bindings: reset: Document canaan, k210-rst bindings Date: Wed, 2 Dec 2020 12:24:47 +0900 Message-Id: <20201202032500.206346-9-damien.lemoal@wdc.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201202032500.206346-1-damien.lemoal@wdc.com> References: <20201202032500.206346-1-damien.lemoal@wdc.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Document the device tree bindings for the Canaan Kendryte K210 SoC reset controller driver in Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml. The header file include/dt-bindings/reset/k210-rst.h is added to define all possible reset lines of the SoC. Signed-off-by: Damien Le Moal --- .../bindings/reset/canaan,k210-rst.yaml | 40 ++++++++++++++++++ include/dt-bindings/reset/k210-rst.h | 42 +++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml create mode 100644 include/dt-bindings/reset/k210-rst.h diff --git a/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml new file mode 100644 index 000000000000..53e4ede9c0bd --- /dev/null +++ b/Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/canaan,k210-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K210 Reset Controller Device Tree Bindings + +maintainers: + - Damien Le Moal + +description: | + Canaan Kendryte K210 reset controller driver which supports the SoC + system controller supplied reset registers for the various peripherals + of the SoC. The K210 reset controller node must be defined as a child + node of the K210 system controller node. + + See also: + - dt-bindings/reset/k210-rst.h + +properties: + compatible: + const: canaan,k210-rst + + '#reset-cells': + const: 1 + +required: + - '#reset-cells' + - compatible + +additionalProperties: false + +examples: + - | + #include + sysrst: reset-controller { + compatible = "canaan,k210-rst"; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/reset/k210-rst.h b/include/dt-bindings/reset/k210-rst.h new file mode 100644 index 000000000000..883c1aed50e8 --- /dev/null +++ b/include/dt-bindings/reset/k210-rst.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Sean Anderson + * Copyright (c) 2020 Western Digital Corporation or its affiliates. + */ +#ifndef RESET_K210_SYSCTL_H +#define RESET_K210_SYSCTL_H + +/* + * Kendryte K210 SoC system controller K210_SYSCTL_SOFT_RESET register bits. + * Taken from Kendryte SDK (kendryte-standalone-sdk). + */ +#define K210_RST_ROM 0 +#define K210_RST_DMA 1 +#define K210_RST_AI 2 +#define K210_RST_DVP 3 +#define K210_RST_FFT 4 +#define K210_RST_GPIO 5 +#define K210_RST_SPI0 6 +#define K210_RST_SPI1 7 +#define K210_RST_SPI2 8 +#define K210_RST_SPI3 9 +#define K210_RST_I2S0 10 +#define K210_RST_I2S1 11 +#define K210_RST_I2S2 12 +#define K210_RST_I2C0 13 +#define K210_RST_I2C1 14 +#define K210_RST_I2C2 15 +#define K210_RST_UART1 16 +#define K210_RST_UART2 17 +#define K210_RST_UART3 18 +#define K210_RST_AES 19 +#define K210_RST_FPIOA 20 +#define K210_RST_TIMER0 21 +#define K210_RST_TIMER1 22 +#define K210_RST_TIMER2 23 +#define K210_RST_WDT0 24 +#define K210_RST_WDT1 25 +#define K210_RST_SHA 26 +#define K210_RST_RTC 29 + +#endif /* RESET_K210_SYSCTL_H */