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[92.34.215.146]) by smtp.gmail.com with ESMTPSA id c9sm3301534lfd.98.2020.11.17.13.35.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Nov 2020 13:35:53 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Bartosz Golaszewski , Linus Walleij , Yash Shah , "Wesley W . Terpstra" , Marc Zyngier Subject: [PATCH 1/2 v1] gpio: sifive: Set affinity callback to parent Date: Tue, 17 Nov 2020 22:33:50 +0100 Message-Id: <20201117213351.249668-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This assigns the .irq_set_affinity to the parent callback. I assume the sifive GPIO can be used in systems with SMP. I used the pattern making the hirerarchy tolerant for missing parent as in Marc's earlier patches. Cc: Yash Shah Cc: Wesley W. Terpstra Suggested-by: Marc Zyngier Signed-off-by: Linus Walleij --- ChangeLog RFT->v1: - Make the affinity setting call return -EINVAL if there is no parent. - Real patch because now we believe in this --- drivers/gpio/gpio-sifive.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.26.2 diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c index c54dd08f2cbf..485820e4488c 100644 --- a/drivers/gpio/gpio-sifive.c +++ b/drivers/gpio/gpio-sifive.c @@ -128,6 +128,16 @@ static void sifive_gpio_irq_eoi(struct irq_data *d) irq_chip_eoi_parent(d); } +static int sifive_gpio_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, + bool force) +{ + if (data->parent_data) + return irq_chip_set_affinity_parent(data, dest, force); + + return -EINVAL; +} + static struct irq_chip sifive_gpio_irqchip = { .name = "sifive-gpio", .irq_set_type = sifive_gpio_irq_set_type, @@ -136,6 +146,7 @@ static struct irq_chip sifive_gpio_irqchip = { .irq_enable = sifive_gpio_irq_enable, .irq_disable = sifive_gpio_irq_disable, .irq_eoi = sifive_gpio_irq_eoi, + .irq_set_affinity = sifive_gpio_irq_set_affinity, }; static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc,