From patchwork Fri Aug 7 07:49:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiyong Tao X-Patchwork-Id: 254654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.4 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6E1FAC433E0 for ; Fri, 7 Aug 2020 07:50:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4594B22CAE for ; Fri, 7 Aug 2020 07:50:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="smOkKvXl" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726980AbgHGHuF (ORCPT ); Fri, 7 Aug 2020 03:50:05 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:8721 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726212AbgHGHuD (ORCPT ); Fri, 7 Aug 2020 03:50:03 -0400 X-UUID: fbf1fc8762564f7098fd1df0e4cfc471-20200807 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EZxnpJDS0ELqN2uc/Zq3rprsvYv0d8wUv0E50ciolpY=; b=smOkKvXlu/PhHL5aKUBZ/pH922mh9wklUmMjl1QqP8zniT13p7dMhgovsg0xEZ1yv17x8RmepWPI60tZG4myJcfpxgIifQ3gATM658fD9810JNxvcsXWCWgW8z3kjObQmsDYMYsxr0WXCF37noagolmvot/31SUg4Px+2kw+ytM=; X-UUID: fbf1fc8762564f7098fd1df0e4cfc471-20200807 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1583015800; Fri, 07 Aug 2020 15:49:55 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 7 Aug 2020 15:49:53 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 7 Aug 2020 15:49:51 +0800 From: Zhiyong Tao To: , , , , CC: , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/3] dt-bindings: pinctrl: mt8192: add binding document Date: Fri, 7 Aug 2020 15:49:04 +0800 Message-ID: <20200807074905.23468-3-zhiyong.tao@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20200807074905.23468-1-zhiyong.tao@mediatek.com> References: <20200807074905.23468-1-zhiyong.tao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The commit adds mt8192 compatible node in binding document. Signed-off-by: Zhiyong Tao --- .../bindings/pinctrl/pinctrl-mt8192.yaml | 149 ++++++++++++++++++ 1 file changed, 149 insertions(+) create mode 100755 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml -- 2.18.0 diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml new file mode 100755 index 000000000000..3b46bbfa38ec --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8192 Pin Controller + +maintainers: + - Sean Wang + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8192-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: gpio valid number range. + maxItems: 1 + + reg: + description: | + Physical address base for gpio base registers. There are 11 GPIO + physical address base in mt8192. + maxItems: 11 + + reg-names: + description: | + Gpio base register names. + maxItems: 11 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^pins': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + state_0_node_a { + pinmux = ; + }; + /* GPIO1 set as multifunction PWM */ + state_0_node_a { + pinmux = ; + }; + }; + properties: + pinmux: + $ref: "pinmux-node.yaml" + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. + + drive-strength: + description: | + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + };