From patchwork Mon Apr 13 11:18:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 207075 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB897C2BA19 for ; Mon, 13 Apr 2020 11:23:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A06DE2075E for ; Mon, 13 Apr 2020 11:23:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728950AbgDMLSa (ORCPT ); Mon, 13 Apr 2020 07:18:30 -0400 Received: from mga17.intel.com ([192.55.52.151]:29256 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728096AbgDMLS3 (ORCPT ); Mon, 13 Apr 2020 07:18:29 -0400 IronPort-SDR: CuffnDMvIj+6yMCu5FiwMknSSYb7jxzVQux6kJnppetYUTuLX6wE7WqVtaM6NseGmfsxxnOfw3 j9Jv9BzZyx5A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Apr 2020 04:18:29 -0700 IronPort-SDR: pYqj3Ue39Q9e1dkHAkeTz4DE/z43ZnK7+eYVSb0uBaSeX+lNrk71zRbRjhXdAoChe8LytN8NFw +ghB8KXvCXeg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,378,1580803200"; d="scan'208";a="243513196" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 13 Apr 2020 04:18:28 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 554F8E1; Mon, 13 Apr 2020 14:18:27 +0300 (EEST) From: Andy Shevchenko To: Mika Westerberg , linux-gpio@vger.kernel.org, Linus Walleij Cc: Andy Shevchenko Subject: [PATCH v2 3/6] pinctrl: icelake: Use generic flag for special GPIO base treatment Date: Mon, 13 Apr 2020 14:18:22 +0300 Message-Id: <20200413111825.89866-3-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200413111825.89866-1-andriy.shevchenko@linux.intel.com> References: <20200413111825.89866-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko --- v2: no changes drivers/pinctrl/intel/pinctrl-icelake.c | 30 ++++++++++++------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 6489e9bbb61f..429b5a83acf0 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -29,8 +29,6 @@ .gpio_base = (g), \ } -#define ICL_NO_GPIO -1 - #define ICL_COMMUNITY(b, s, e, g) \ { \ .barno = (b), \ @@ -305,29 +303,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = { }; static const struct intel_padgroup icllp_community0_gpps[] = { - ICL_GPP(0, 0, 7, 0), /* GPP_G */ - ICL_GPP(1, 8, 33, 32), /* GPP_B */ - ICL_GPP(2, 34, 58, 64), /* GPP_A */ + ICL_GPP(0, 0, 7, 0), /* GPP_G */ + ICL_GPP(1, 8, 33, 32), /* GPP_B */ + ICL_GPP(2, 34, 58, 64), /* GPP_A */ }; static const struct intel_padgroup icllp_community1_gpps[] = { - ICL_GPP(0, 59, 82, 96), /* GPP_H */ - ICL_GPP(1, 83, 103, 128), /* GPP_D */ - ICL_GPP(2, 104, 123, 160), /* GPP_F */ - ICL_GPP(3, 124, 152, 192), /* vGPIO */ + ICL_GPP(0, 59, 82, 96), /* GPP_H */ + ICL_GPP(1, 83, 103, 128), /* GPP_D */ + ICL_GPP(2, 104, 123, 160), /* GPP_F */ + ICL_GPP(3, 124, 152, 192), /* vGPIO */ }; static const struct intel_padgroup icllp_community4_gpps[] = { - ICL_GPP(0, 153, 176, 224), /* GPP_C */ - ICL_GPP(1, 177, 182, ICL_NO_GPIO), /* HVCMOS */ - ICL_GPP(2, 183, 206, 256), /* GPP_E */ - ICL_GPP(3, 207, 215, ICL_NO_GPIO), /* JTAG */ + ICL_GPP(0, 153, 176, 224), /* GPP_C */ + ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ICL_GPP(2, 183, 206, 256), /* GPP_E */ + ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup icllp_community5_gpps[] = { - ICL_GPP(0, 216, 223, 288), /* GPP_R */ - ICL_GPP(1, 224, 231, 320), /* GPP_S */ - ICL_GPP(2, 232, 240, ICL_NO_GPIO), /* SPI */ + ICL_GPP(0, 216, 223, 288), /* GPP_R */ + ICL_GPP(1, 224, 231, 320), /* GPP_S */ + ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community icllp_communities[] = {