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[213.113.123.174]) by smtp.gmail.com with ESMTPSA id q128-v6sm431515ljq.72.2018.08.22.13.41.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 13:41:35 -0700 (PDT) From: Linus Walleij To: H Hartley Sweeten , Alexander Sverdlin Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Linus Walleij Subject: [PATCH 07/11] gpio: ep93xx: Do not pingpong irq numbers Date: Wed, 22 Aug 2018 22:41:07 +0200 Message-Id: <20180822204111.9581-8-linus.walleij@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180822204111.9581-1-linus.walleij@linaro.org> References: <20180822204111.9581-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org For setting debounce config we want to write an offset in a per-gpiochip register, and we know which gpiochip we are on. Instead of a roundtrip over the IRQ number, figure out what port we are on for this GPIO chip, then index to the right register and write the value. This adds the ep93xx_gpio_port() that finds the port index from a struct gpio_chip * that we can later exploit to simplify more code. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ep93xx.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/gpio/gpio-ep93xx.c b/drivers/gpio/gpio-ep93xx.c index ce7e88df9cc5..3b235b25c028 100644 --- a/drivers/gpio/gpio-ep93xx.c +++ b/drivers/gpio/gpio-ep93xx.c @@ -68,12 +68,29 @@ static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg, unsigned port epg->base + int_en_register_offset[port]); } -static void ep93xx_gpio_int_debounce(struct ep93xx_gpio *epg, - unsigned int irq, bool enable) +static int ep93xx_gpio_port(struct gpio_chip *gc) { - int line = irq_to_gpio(irq); - int port = line >> 3; - int port_mask = 1 << (line & 7); + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int port = 0; + + while (gc != &epg->gc[port] && port < sizeof(epg->gc)) + port++; + + /* This should not happen but is there as a last safeguard */ + if (gc != &epg->gc[port]) { + pr_crit("can't find the GPIO port\n"); + return 0; + } + + return port; +} + +static void ep93xx_gpio_int_debounce(struct gpio_chip *gc, + unsigned int offset, bool enable) +{ + struct ep93xx_gpio *epg = gpiochip_get_data(gc); + int port = ep93xx_gpio_port(gc); + int port_mask = BIT(offset); if (enable) gpio_int_debounce[port] |= port_mask; @@ -331,19 +348,13 @@ static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset, unsigned long config) { - struct ep93xx_gpio *epg = gpiochip_get_data(gc); - int gpio = gc->base + offset; - int irq = gpio_to_irq(gpio); u32 debounce; if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) return -ENOTSUPP; - if (irq < 0) - return -EINVAL; - debounce = pinconf_to_config_argument(config); - ep93xx_gpio_int_debounce(epg, irq, debounce ? true : false); + ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false); return 0; }