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[209.132.180.67]) by mx.google.com with ESMTP id z9si4038677pgo.720.2018.03.18.17.51.23; Sun, 18 Mar 2018 17:51:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MhsUmkSh; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754783AbeCSAvX (ORCPT + 5 others); Sun, 18 Mar 2018 20:51:23 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:42233 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754673AbeCSAvW (ORCPT ); Sun, 18 Mar 2018 20:51:22 -0400 Received: by mail-pl0-f67.google.com with SMTP id w15-v6so9234089plq.9 for ; Sun, 18 Mar 2018 17:51:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nk2wOdMgCJGVpiNdGoWHc35KZQzo7+X+MGbaEETaTcE=; b=MhsUmkShhTS2y3X64Rds0O3YVcG5WDJ7ztUV8vmiJj9924RoIpzpFchZ75ohqjTk2k YggtiANk0y2kRv2glYGaJ3qE53/s2slQKdsC5bc7/Y50IWy4TyOPUlidiBun9T9/INRn nhPu7+BDL50yfs1CDsgp+ozhJXAfRFdc7J6tc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nk2wOdMgCJGVpiNdGoWHc35KZQzo7+X+MGbaEETaTcE=; b=L5sE7lmdz0XOQ54ZoIsN9pNdM31GAeGHHuqw1kf5EGAvSq9CVfMwZ5DdBnHlzhmPs+ 8cFWjlD1mpeX4GZ1CULxg33olO7yBxeXy6QaEKoyJ/xlQB+Wp22E2mO1b07qMjjYdljj t47dX6g4pQLpCrMLJX+0s4oFcRMLz8zoDCyLyft0Z1zzp4WBZRvdTJsYyY3Kcf2bUKbC bwPswakTDvaS1r7+omrtH0l+HnApbEHNAn2DqLDLuE44ycgXWiWisdl3uaN8pKgD3LpK zIk1Gt+Au0dWk7nygktldM20y+Y1kCq9PoWqAFeu9Xh0dDZtBJPcBxfRGbKnMK2DaOpS Z8cQ== X-Gm-Message-State: AElRT7H2/XruPuaU57WKvZuLgdcwNrBRw3h58AJiO4Cb0RgiKEq/N+Db T3/GaCY9XrhETs0kRJU8GTQBvtd1evPMcg== X-Received: by 2002:a17:902:22a:: with SMTP id 39-v6mr10609808plc.128.1521420682113; Sun, 18 Mar 2018 17:51:22 -0700 (PDT) Received: from localhost.localdomain ([218.255.99.6]) by smtp.gmail.com with ESMTPSA id z15sm21766373pgr.68.2018.03.18.17.51.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 18 Mar 2018 17:51:21 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Linus Walleij Subject: [PATCH 08/13] gpio: ich: Use BIT() macro Date: Mon, 19 Mar 2018 01:50:51 +0100 Message-Id: <20180319005056.7380-8-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180319005056.7380-1-linus.walleij@linaro.org> References: <20180319005056.7380-1-linus.walleij@linaro.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Using BIT() makes (1 << foo) constructions easier to read, and also account for common mistakes where bit 31 is not working because of numbers being interpreted as negative unless specified as unsigned. Signed-off-by: Linus Walleij --- drivers/gpio/gpio-ich.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/gpio/gpio-ich.c b/drivers/gpio/gpio-ich.c index 7a54165d7276..dba392221042 100644 --- a/drivers/gpio/gpio-ich.c +++ b/drivers/gpio/gpio-ich.c @@ -26,6 +26,7 @@ #include #include #include +#include #define DRV_NAME "gpio_ich" @@ -131,9 +132,9 @@ static int ichx_write_bit(int reg, unsigned nr, int val, int verify) ichx_priv.gpio_base); if (val) - data |= 1 << bit; + data |= BIT(bit); else - data &= ~(1 << bit); + data &= ~BIT(bit); ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], ichx_priv.gpio_base); if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) @@ -166,12 +167,12 @@ static int ichx_read_bit(int reg, unsigned nr) spin_unlock_irqrestore(&ichx_priv.lock, flags); - return data & (1 << bit) ? 1 : 0; + return !!(data & BIT(bit)); } static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) { - return !!(ichx_priv.use_gpio & (1 << (nr / 32))); + return !!(ichx_priv.use_gpio & BIT(nr / 32)); } static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) @@ -232,12 +233,12 @@ static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) spin_lock_irqsave(&ichx_priv.lock, flags); /* GPI 0 - 15 are latched, write 1 to clear*/ - ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base); + ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); data = ICHX_READ(0, ichx_priv.pm_base); spin_unlock_irqrestore(&ichx_priv.lock, flags); - return (data >> 16) & (1 << nr) ? 1 : 0; + return !!((data >> 16) & BIT(nr)); } else { return ichx_gpio_get(chip, nr); } @@ -254,7 +255,7 @@ static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) * the chipset's USE value can be trusted for this specific bit. * If it can't be trusted, assume that the pin can be used as a GPIO. */ - if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f))) + if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) return 0; return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; @@ -394,7 +395,7 @@ static int ichx_gpio_request_regions(struct device *dev, return -ENODEV; for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { - if (!(use_gpio & (1 << i))) + if (!(use_gpio & BIT(i))) continue; if (!devm_request_region(dev, res_base->start + ichx_priv.desc->regs[0][i],