From patchwork Wed Oct 25 12:05:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mukesh Ojha X-Patchwork-Id: 738532 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 022FEC07545 for ; Wed, 25 Oct 2023 12:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234812AbjJYMFb (ORCPT ); Wed, 25 Oct 2023 08:05:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234811AbjJYMF3 (ORCPT ); Wed, 25 Oct 2023 08:05:29 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF20E129; Wed, 25 Oct 2023 05:05:27 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39PAcYgi012244; Wed, 25 Oct 2023 12:05:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=vyQecuOeIjnpfvPPigrXzUOcLJ/f+FhVUGhffoBskJg=; b=XBkZVQ/wi3nM9ycUdH3vjGCw3/MdW0J1QLPxrwLQE16ORBwBCUe20+9HGPfoYfx/CSIV VxKVpMCPkUQcK2etAIKhy9KYjW5kQg50NtgGacTGN2vhK3SY/iyvSeOo7AkrKvmGmmp6 bahT0aQU3ToYxvMFbdMxDSDmyYSTeRw7pFuLeIG/HKnepEGwvBXldDNGDdZx3ZDGlPy9 bBxRsITQwpfH1Qi6/vG/NJKEFfRsp7Zviy4DE2ajkHwKAf1G/UOhbXsSGKUs/rWbegwT O5ZB0xm5WLeUuB7brSQ3L5x9gUG8xwS9wFmUeOjpj8DcHxFfxHQQHLVLVWTdHY4DxC8R DA== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3txngvher1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:22 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39PC5LLL004621 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Oct 2023 12:05:21 GMT Received: from hu-mojha-hyd.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 25 Oct 2023 05:05:19 -0700 From: Mukesh Ojha To: , , , CC: , , , Mukesh Ojha Subject: [PATCH v8 1/3] firmware: qcom_scm: provide a read-modify-write function Date: Wed, 25 Oct 2023 17:35:04 +0530 Message-ID: <1698235506-16993-2-git-send-email-quic_mojha@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> References: <1698235506-16993-1-git-send-email-quic_mojha@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bu1smIRz_zTzZpzVLpcAQ66OOdUZE5sd X-Proofpoint-ORIG-GUID: bu1smIRz_zTzZpzVLpcAQ66OOdUZE5sd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-25_01,2023-10-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 malwarescore=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 mlxlogscore=874 impostorscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310170001 definitions=main-2310250104 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org It was realized by Srinivas K. that there is a need of read-modify-write scm exported function so that it can be used by multiple clients. Let's introduce qcom_scm_io_rmw() which masks out the bits and write the passed value to that bit-offset. Suggested-by: Srinivas Kandagatla Signed-off-by: Mukesh Ojha Tested-by: Kathiravan Thirumoorthy # IPQ9574 and IPQ5332 --- drivers/firmware/qcom/qcom_scm.c | 26 ++++++++++++++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c index 520de9b5633a..25549178a30f 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -41,6 +42,8 @@ struct qcom_scm { int scm_vote_count; u64 dload_mode_addr; + /* Atomic context only */ + spinlock_t lock; }; struct qcom_scm_current_perm_info { @@ -481,6 +484,28 @@ static int qcom_scm_disable_sdi(void) return ret ? : res.result[0]; } +int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val) +{ + unsigned int old, new; + int ret; + + if (!__scm) + return -EINVAL; + + spin_lock(&__scm->lock); + ret = qcom_scm_io_readl(addr, &old); + if (ret) + goto unlock; + + new = (old & ~mask) | (val & mask); + + ret = qcom_scm_io_writel(addr, new); +unlock: + spin_unlock(&__scm->lock); + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_io_rmw); + static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { struct qcom_scm_desc desc = { @@ -1824,6 +1849,7 @@ static int qcom_scm_probe(struct platform_device *pdev) return ret; mutex_init(&scm->scm_bw_lock); + spin_lock_init(&scm->lock); scm->path = devm_of_icc_get(&pdev->dev, NULL); if (IS_ERR(scm->path)) diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index ccaf28846054..3a8bb2e603b3 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -82,6 +82,7 @@ bool qcom_scm_pas_supported(u32 peripheral); int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); +int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val); bool qcom_scm_restore_sec_cfg_available(void); int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);