From patchwork Thu Sep 17 05:33:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 254366 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0C1CC433E2 for ; Thu, 17 Sep 2020 05:49:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B64020872 for ; Thu, 17 Sep 2020 05:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726186AbgIQFtA (ORCPT ); Thu, 17 Sep 2020 01:49:00 -0400 Received: from inva021.nxp.com ([92.121.34.21]:39130 "EHLO inva021.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726109AbgIQFs7 (ORCPT ); Thu, 17 Sep 2020 01:48:59 -0400 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 296F3200C75; Thu, 17 Sep 2020 07:40:58 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A1B42200BFD; Thu, 17 Sep 2020 07:40:47 +0200 (CEST) Received: from 10.192.242.69 (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 684FA40310; Thu, 17 Sep 2020 07:40:32 +0200 (CEST) From: Anson Huang To: linux@armlinux.org.uk, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, catalin.marinas@arm.com, will@kernel.org, linus.walleij@linaro.org, bgolaszewski@baylibre.com, oleksandr.suvorov@toradex.com, peng.fan@nxp.com, andreas@kemnade.info, hverkuil-cisco@xs4all.nl, olof@lixom.net, krzk@kernel.org, geert+renesas@glider.be, prabhakar.mahadev-lad.rj@bp.renesas.com, aisheng.dong@nxp.com, lkundrak@v3.sk, joel@jms.id.au, bjorn.andersson@linaro.org, leoyang.li@nxp.com, vkoul@kernel.org, michael@walle.cc, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org Cc: Linux-imx@nxp.com Subject: [PATCH V3 2/4] arm64: defconfig: Build in CONFIG_GPIO_MXC by default Date: Thu, 17 Sep 2020 13:33:47 +0800 Message-Id: <1600320829-1453-2-git-send-email-Anson.Huang@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600320829-1453-1-git-send-email-Anson.Huang@nxp.com> References: <1600320829-1453-1-git-send-email-Anson.Huang@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org i.MX SoC GPIO driver provides the basic functions of GPIO pin operations and IRQ operations, it is now changed from "def_bool y" to "tristate", so it should be explicitly enabled to make sure all consumers work normally. Signed-off-by: Anson Huang --- changes since V2: - improve commit message to explain why CONFIG_GPIO_MXC needs to be enabled. --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 63003ec..c8fca1a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -510,6 +510,7 @@ CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_BD9571MWV=m CONFIG_GPIO_MAX77620=y +CONFIG_GPIO_MXC=y CONFIG_POWER_AVS=y CONFIG_QCOM_CPR=y CONFIG_ROCKCHIP_IODOMAIN=y