From patchwork Fri Feb 8 12:33:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 157836 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp1899698jaa; Fri, 8 Feb 2019 04:32:26 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia3Aq6P0PpYacz6MyBDvC9MmpAI61K/HSrIzHQ6uIpP+pL71MpoiTwBsIwgtfyoaLfWF9cs X-Received: by 2002:a17:902:b83:: with SMTP id 3mr21634921plr.42.1549629146220; Fri, 08 Feb 2019 04:32:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549629146; cv=none; d=google.com; s=arc-20160816; b=knfE9LhOr8PvWDNm+httO1/Vk6CcvUuoDEBRKwFBbljJvJ4Y7GLubCreYLoGAtKPKi A9uQN3B8yT9YdhtvTUtioB6tbQKhyDQ/T938sEvvEu7NcAWoLAc1Wmz4ltxWC53mLXoK 0uhsE8LEboZA1U9lyogyKjk7gq9byZ4STkSfNPkFMB5FBwwXrhPpoGGq5amx43jTtbzJ Ky3Ca2immjrprrZHEH+G9rV/InbUVz5uK0N+2LvqEgJYjYic9XXfDzpgpjm44ULr0afB 301ewy94zGYf/Ju2e4WAFXgb6TGvs9pR3a9r6zczon8fbPQyuCJHYCxvQimPIjMYO2DC VjNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=q/P5douetbYr2+wlF3vHyRbITISD/MCy29HzbjGUfqw=; b=Wm64R/27AJVcIuVqDb6w0iRT9HDgdEYAuqHbVrhVEa4Iw7hd7h40ELvLPBm47wHUIw 3T+4hOGgks0Lrjo/I7LUhbhjsb4mlR8/5boLn40rqauTvmXjD0/9uNZD7cHKRqQ0kRwB tOyn/jtL4NlrT65gekyG1tA2fkdc8AcPCYr019VE+gT+UZteBjxj4gZsJYIvQUyeWUBZ TKbKOiGelg1RtobMyCbzzBoAUrp1lWbvtHDnD2ah+Ps82Uz3+T/L+1IHX0iepTnRNBz2 fTjBeFJmV23jb6QzrH6nB0cFpiC+8mFYkOyIAc/IixQ1ZCyXyIa9mGS4eSxuVRCXJZCy de9A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c7si2042684pgg.339.2019.02.08.04.32.25; Fri, 08 Feb 2019 04:32:26 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726747AbfBHMcZ (ORCPT + 5 others); Fri, 8 Feb 2019 07:32:25 -0500 Received: from mx.socionext.com ([202.248.49.38]:27866 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726703AbfBHMcZ (ORCPT ); Fri, 8 Feb 2019 07:32:25 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:32:23 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 26F8560062; Fri, 8 Feb 2019 21:32:23 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:32:23 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id E6D174036D; Fri, 8 Feb 2019 21:32:22 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id CDC701202F1; Fri, 8 Feb 2019 21:32:22 +0900 (JST) From: Sugaya Taichi To: linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Linus Walleij , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v2 11/15] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Date: Fri, 8 Feb 2019 21:33:07 +0900 Message-Id: <1549629187-3177-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add DT bindings document for Milbeaut M10V pinctrl. Signed-off-by: Sugaya Taichi --- .../pinctrl/socionext,milbeaut-pinctrl.txt | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt new file mode 100644 index 0000000..6b54191 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt @@ -0,0 +1,35 @@ +Milbeaut SoCs pin controller + +Required properties: +- compatible: should be one of the following: + "socionext,milbeaut-m10v-pinctrl" - for m10v SoC +- reg: offset and length of the register set. +- reg-names: should be "pinctrl", "exiu". +- gpio-controller: marks the device node as a gpio controller. +- gpio-cells: should be 2. +- interrupt-controller: marks the device node as a interrupt controller. +- interrupt-cells: should be 2. +- clocks: phandle to the input clock. +- interrupts: three interrupts specifer. +- interrupt-names: corresponds "interrupts" factor. + +Example: + pinctrl: pinctrl@1d022000 { + compatible = "socionext,milbeaut-m10v-pinctrl"; + reg = <0x1d022000 0x1000>, + <0x1c26f000 0x1000>; + reg-names = "pinctrl", "exiu"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk 2>; + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>, + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>, + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>, + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>; + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51", + "pin-52", "pin-53", "pin-54", "pin-55", + "pin-56", "pin-57", "pin-58", "pin-59", + "pin-60", "pin-61", "pin-62", "pin-63"; + }