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[209.132.180.67]) by mx.google.com with ESMTP id a9si20997207pao.113.2016.08.26.05.19.49; Fri, 26 Aug 2016 05:19:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751668AbcHZMTs (ORCPT + 4 others); Fri, 26 Aug 2016 08:19:48 -0400 Received: from mail-pf0-f179.google.com ([209.85.192.179]:33063 "EHLO mail-pf0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751168AbcHZMTs (ORCPT ); Fri, 26 Aug 2016 08:19:48 -0400 Received: by mail-pf0-f179.google.com with SMTP id y134so28334481pfg.0 for ; Fri, 26 Aug 2016 05:19:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=aBm2WGKWq9g6kwgY/OSIPMvbs5xjy6sKmji1Cs2KXi0=; b=Y7BDk6cQLsb4WQ/xLUB4HXlHSeEwoiPcMoePQ1TP5g7W8pRymrY/rHgzDz0lyxRAOs hVuXvolNGc0sdvaEE5CraqMZ9VzixkFFxI+h287m2bMx2G/nLOmaRElDaJ61dU0bfH9y c6ZgEb5odMyXUClyeGvUgaskwLcs9LSBxRB7c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=aBm2WGKWq9g6kwgY/OSIPMvbs5xjy6sKmji1Cs2KXi0=; b=FM0ZK8T3FAb1OT7pv/2mlxo+C/cuKKGJhbvH+Z+mU1lTabU5kk8gyFZJ1HHr3y3s2R gXdeEdT4Hpmj3DbOehdVaxHL1XhAyTZjC4ad1XC6cMDVeWj/qtGeGe6kLTLuPwEBDm3Q SLRLolMoXWovMi5fnnyS378qvDyidprJJ9LKS4wYAl/LxUp/l0C/OA5kvWbzQQE51PMH APMgIXgr0TlVsAcSu1kSVJVQNbVe7ILdcSBu+SX068s2MWtYC65zzui238TXYVBFmwm+ d6w6RBQP0fm/sZWTTOYIbSlnk7T4avlW0QzmwB7D8QvR4yMfOFBiuls2BXMBdgiHzNrE 1fkQ== X-Gm-Message-State: AE9vXwO4U09/rUJz7LC7+yzSSL39HJIuAC1smr7+T+faB4lEAoRKSA5QCrI8FLS0eEt100yA X-Received: by 10.98.63.1 with SMTP id m1mr5601200pfa.14.1472213987674; Fri, 26 Aug 2016 05:19:47 -0700 (PDT) Received: from localhost.localdomain ([104.237.91.147]) by smtp.gmail.com with ESMTPSA id d3sm28444413pfk.37.2016.08.26.05.19.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 26 Aug 2016 05:19:47 -0700 (PDT) From: Jun Nie To: linus.walleij@linaro.org, linux-gpio@vger.kernel.org Cc: shawn.guo@linaro.org, jason.liu@linaro.org, Jun Nie Subject: [PATCH 2/3] pinctrl: zx: Add ZTE pinctrl dts document Date: Fri, 26 Aug 2016 20:19:24 +0800 Message-Id: <1472213965-4899-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add initial ZTE pinctrl dts document for ZX296718 SoC. Signed-off-by: Jun Nie --- .../devicetree/bindings/pinctrl/pinctrl-zx.txt | 54 ++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt new file mode 100644 index 0000000..4061f51 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-zx.txt @@ -0,0 +1,54 @@ +* ZTE ZX Pin Controller + +The pins controlled by ZX pin controller are organized in banks, +number of pins in each bank may vary. Each pin has different multiplexing +functions. There are two type of pins, normal ones and AON ones. AON +pins control high level multiplex and normal pins may require multiplex +configuration of parent AON pins. As the AON pins number is not as much as +normal pins, some normal pins are not routed through AON pin side and are +under direct control by itself. + +Required properties: +- compatible: + "zte,zx296718-pinctrl" + "zte,zx296718-aonpmx" + +- reg: Should contain the register physical address and length for the + pin controller. + +IO pull up/down etc configuration is supported with unified management of +normal pins and AON pins. The configuration registers area is just after +AON pinmux reg area, while normal pins regs in different area. So two dts +nodes are needed to provides the two reg regions. + +Below configuration are supported. Please refer to pinctrl-bindings.txt +in this directory for more details of the common pinctrl bindings used +by client devices. + +bias-pull-up - pull up the pin +bias-pull-down - pull down the pin +drive-strength - sink or source at most 7 mA +input-enable - enable input on pin (no effect on output) +power-source - select power supplies. 1: 1.8V, 0: 3.3V +slew-rate - set the slew rate + +Pin names are defined by bank sequence and pins number in the bank. For +example, B2 is the 3rd pin in the second bank. The AON pin has prefix +AON, like AONC2. + +Example dts nodes: + +pinctop: pinctrl@01462000 { + compatible = "zte,zx296718-pinctrl"; + reg = <0x01462000 0x1000>; + + i2c5_pins: i2c5pins { + pins = "G6", "G7"; + function = "I2C5"; + } +}; + +pmx_aon: pinctrl@00119000 { + compatible = "zte,zx296718-aonpmx"; + reg = <0x00119000 0x1000>; +};