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[209.132.180.67]) by mx.google.com with ESMTP id r20si12813275pfa.51.2015.12.09.05.30.49; Wed, 09 Dec 2015 05:30:49 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro-org.20150623.gappssmtp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754449AbbLINas (ORCPT + 4 others); Wed, 9 Dec 2015 08:30:48 -0500 Received: from mail-lf0-f43.google.com ([209.85.215.43]:36813 "EHLO mail-lf0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754444AbbLINar (ORCPT ); Wed, 9 Dec 2015 08:30:47 -0500 Received: by lfs39 with SMTP id 39so34417582lfs.3 for ; Wed, 09 Dec 2015 05:30:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=+/pcUNXZ9kteB1rFYZ+sNmolKG9GM+sJJyVQ8QfHa6I=; b=0KI7IDWPjdHAplZr6cFJehPNdUhn30HAiMeplnx1ufyt2VTsay4yfRDZ3yDiBVhxVj wEGiao66E4bBisNjuxKh0MnPqDwEacc1FuqXdExjLTEzHbgrmuJxqCRZsOi5zVTakhGS aUctocONarB0mYf/NvhMlhE7Y5oMoLXdI4LOd/wbRLd01eugaCxbSAUYntge2wyDE8Ks ioxy10COMP0PNmo1EIJUPA9t3elv1zK/S0XGEqu4gMoLdxUIor7H/Xwc35L+Smf7X1mE x0l7Iy6vVt6JTLLsS+jO32xTprac3l9gPs5F8GzLNgbX3tRm6dq7WkTrj/VPsPlLsREX JU8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+/pcUNXZ9kteB1rFYZ+sNmolKG9GM+sJJyVQ8QfHa6I=; b=lFB8ukxCLOJDfTTLuWCefs02Rtu+tbI2+wfFToQOSVvd98FBH3v6fy47rBmF54Xifs A5IFVquXSkAVE3/NE8bnth14ZbJHFqwcJB0c+kqq14sDOcr9Ol8beyW/hF6nsXNleLX9 yIPmmzE110i8zyCWdxqkgq6jPw4Z+pLdZsF+dYVWRXi2pC0fV9MISt5hlO7JjX51wQsu Y+ku7wBAviX+5gqK4rh+vvuG6xWZPuUKkXZ81Z788Qp4uRXZ5niQap/+4N6dpM1MUqoD HVTsDBHB9U4Zz0aJxKGTccOzEz3ys+ptEeUBZDQtR/xbykn/456pMOWhYJtZ8qMvlxIm Wi9g== X-Gm-Message-State: ALoCoQno1vSKoB0pw22VntohRQS2RrSp/0kQ4r1CIwuZijTL49CMZ6e5LzoWn1rJWrbk/orryYtFvMTtgj9MXLpFx010d2Ao2g== X-Received: by 10.25.83.146 with SMTP id h140mr2026344lfb.52.1449667846284; Wed, 09 Dec 2015 05:30:46 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id lc3sm1423877lbc.32.2015.12.09.05.30.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Dec 2015 05:30:45 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org, Johan Hovold , Alexandre Courbot , Michael Welling , Markus Pargmann Cc: Linus Walleij , Mika Westerberg , Heikki Krogerus Subject: [PATCH 093/182] pinctrl: cherryview: use gpiochip data pointer Date: Wed, 9 Dec 2015 14:30:43 +0100 Message-Id: <1449667843-1997-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This makes the driver use the data pointer added to the gpio_chip to store a pointer to the state container instead of relying on container_of(). Cc: Mika Westerberg Cc: Heikki Krogerus Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-cherryview.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index dac8ec46aeb4..4251e0747a3a 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -181,8 +181,6 @@ struct chv_pinctrl { struct chv_pin_context *saved_pin_context; }; -#define gpiochip_to_pinctrl(c) container_of(c, struct chv_pinctrl, chip) - #define ALTERNATE_FUNCTION(p, m, i) \ { \ .pin = (p), \ @@ -1157,7 +1155,7 @@ static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl, static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) { - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); + struct chv_pinctrl *pctrl = gpiochip_get_data(chip); int pin = chv_gpio_offset_to_pin(pctrl, offset); unsigned long flags; u32 ctrl0, cfg; @@ -1176,7 +1174,7 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) { - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); + struct chv_pinctrl *pctrl = gpiochip_get_data(chip); unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); unsigned long flags; void __iomem *reg; @@ -1199,7 +1197,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value) static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) { - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); + struct chv_pinctrl *pctrl = gpiochip_get_data(chip); unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); u32 ctrl0, direction; unsigned long flags; @@ -1240,7 +1238,7 @@ static const struct gpio_chip chv_gpio_chip = { static void chv_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + struct chv_pinctrl *pctrl = gpiochip_get_data(gc); int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); u32 intr_line; @@ -1257,7 +1255,7 @@ static void chv_gpio_irq_ack(struct irq_data *d) static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + struct chv_pinctrl *pctrl = gpiochip_get_data(gc); int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d)); u32 value, intr_line; unsigned long flags; @@ -1302,7 +1300,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) */ if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + struct chv_pinctrl *pctrl = gpiochip_get_data(gc); unsigned offset = irqd_to_hwirq(d); int pin = chv_gpio_offset_to_pin(pctrl, offset); irq_flow_handler_t handler; @@ -1334,7 +1332,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) static int chv_gpio_irq_type(struct irq_data *d, unsigned type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + struct chv_pinctrl *pctrl = gpiochip_get_data(gc); unsigned offset = irqd_to_hwirq(d); int pin = chv_gpio_offset_to_pin(pctrl, offset); unsigned long flags; @@ -1407,7 +1405,7 @@ static struct irq_chip chv_gpio_irqchip = { static void chv_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(gc); + struct chv_pinctrl *pctrl = gpiochip_get_data(gc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; u32 intr_line; @@ -1439,7 +1437,7 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->parent = pctrl->dev; chip->base = -1; - ret = gpiochip_add(chip); + ret = gpiochip_add_data(chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed to register gpiochip\n"); return ret;