From patchwork Fri Nov 27 17:20:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep Holla X-Patchwork-Id: 57370 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp1285858lbb; Fri, 27 Nov 2015 09:21:14 -0800 (PST) X-Received: by 10.98.65.2 with SMTP id o2mr49619260pfa.99.1448644874813; Fri, 27 Nov 2015 09:21:14 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v13si17364943pas.84.2015.11.27.09.21.14; Fri, 27 Nov 2015 09:21:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-gpio-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755005AbbK0RVO (ORCPT + 4 others); Fri, 27 Nov 2015 12:21:14 -0500 Received: from foss.arm.com ([217.140.101.70]:50589 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754984AbbK0RVN (ORCPT ); Fri, 27 Nov 2015 12:21:13 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E9A3C49; Fri, 27 Nov 2015 09:20:54 -0800 (PST) Received: from e103737-lin.cambridge.arm.com (e103737-lin.cambridge.arm.com [10.1.207.150]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 21DEC3F2E5; Fri, 27 Nov 2015 09:21:05 -0800 (PST) From: Sudeep Holla To: Linus Walleij , linux-gpio@vger.kernel.org Cc: Sudeep Holla , linux-kernel@vger.kernel.org Subject: [PATCH 1/2] pinctrl: single: Use a separate lockdep class Date: Fri, 27 Nov 2015 17:20:59 +0000 Message-Id: <1448644860-29323-1-git-send-email-sudeep.holla@arm.com> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The single pinmux controller can be cascaded to the other interrupt controllers. Hence when propagating wake-up settings to its parent interrupt controller, there's possiblity of detecting possible recursive locking and getting lockdep warning. This patch avoids this false positive by using a separate lockdep class for this single pinctrl interrupts. Cc: Linus Walleij Cc: linux-gpio@vger.kernel.org Suggested-by: Thomas Gleixner Signed-off-by: Sudeep Holla --- drivers/pinctrl/pinctrl-single.c | 8 ++++++++ 1 file changed, 8 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index ef04b962c3d5..945a7d0f0704 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -255,6 +255,13 @@ static enum pin_config_param pcs_bias[] = { }; /* + * This lock class tells lockdep that irqchip core that this single + * pinctrl can be in a different category than its parents, so it won't + * report false recursion. + */ +static struct lock_class_key pcs_lock_class; + +/* * REVISIT: Reads and writes could eventually use regmap or something * generic. But at least on omaps, some mux registers are performance * critical as they may need to be remuxed every time before and after @@ -1716,6 +1723,7 @@ static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_set_chip_data(irq, pcs_soc); irq_set_chip_and_handler(irq, &pcs->chip, handle_level_irq); + irq_set_lockdep_class(irq, &pcs_lock_class); irq_set_noprobe(irq); return 0;