From patchwork Mon Jul 6 13:57:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jun Nie X-Patchwork-Id: 50764 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f72.google.com (mail-la0-f72.google.com [209.85.215.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id BB599229FC for ; Mon, 6 Jul 2015 13:57:37 +0000 (UTC) Received: by lagx9 with SMTP id x9sf47584846lag.2 for ; Mon, 06 Jul 2015 06:57:36 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:sender:precedence:list-id:x-original-sender :x-original-authentication-results:mailing-list:list-post:list-help :list-archive:list-unsubscribe; bh=QDuRPSAPlGwcpq3pNWW8zX33qZwwzLxQzorner8i3+A=; b=m4WVlsEpa+J1W+Oz5Rapjz2/8mYHRRbVlyIBy6DhJuArkCBdRA6StmxGj1xVZ+HCxb sUPVnsIwwynWXxP2cQsmceGk8k0r3hqiM3OzRz/x9fffUmz+DOsevZw8hJtiEA15eAP4 qmuvtAXDMAA+oPpJtpgyASDrnB//CJMR9ghbqMr5b29VJUYxYCB+raHI8O88cKrSIh10 MB3CQh7U8e458C3MuSZIS96n02sKo1Ez+YaR/T6wZtDcQYvWcXrUb0U8COTQkj7UPSKF P0JiZTJlAx21mnpYw8daCvQfh52Y8++cK0LtZyZY/K0DiZIFgD2R+tDh2lS6aXz9bkwU HujA== X-Gm-Message-State: ALoCoQmBJBcHUGMZTQ2ZfiO/JxMvSKiewS2/ZQFJQxLHiBORYd46zEIKaQbaACJWo5NtIaleaylq X-Received: by 10.112.99.37 with SMTP id en5mr11563038lbb.7.1436191056557; Mon, 06 Jul 2015 06:57:36 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.4.1 with SMTP id g1ls641717lag.46.gmail; Mon, 06 Jul 2015 06:57:36 -0700 (PDT) X-Received: by 10.112.157.100 with SMTP id wl4mr49164229lbb.20.1436191056407; Mon, 06 Jul 2015 06:57:36 -0700 (PDT) Received: from mail-la0-f43.google.com (mail-la0-f43.google.com. [209.85.215.43]) by mx.google.com with ESMTPS id bb9si15326326lab.89.2015.07.06.06.57.36 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Jul 2015 06:57:36 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) client-ip=209.85.215.43; Received: by labgy5 with SMTP id gy5so3480628lab.2 for ; Mon, 06 Jul 2015 06:57:36 -0700 (PDT) X-Received: by 10.152.26.163 with SMTP id m3mr49175178lag.86.1436191056238; Mon, 06 Jul 2015 06:57:36 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.108.230 with SMTP id hn6csp1742482lbb; Mon, 6 Jul 2015 06:57:34 -0700 (PDT) X-Received: by 10.66.66.166 with SMTP id g6mr107083512pat.157.1436191053679; Mon, 06 Jul 2015 06:57:33 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id dy2si29173370pbb.30.2015.07.06.06.57.32; Mon, 06 Jul 2015 06:57:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-gpio-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755485AbbGFN5c (ORCPT + 2 others); Mon, 6 Jul 2015 09:57:32 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:36658 "EHLO mail-pd0-f179.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755351AbbGFN5b (ORCPT ); Mon, 6 Jul 2015 09:57:31 -0400 Received: by pddu5 with SMTP id u5so19132149pdd.3 for ; Mon, 06 Jul 2015 06:57:31 -0700 (PDT) X-Received: by 10.70.130.144 with SMTP id oe16mr3265468pdb.116.1436191051141; Mon, 06 Jul 2015 06:57:31 -0700 (PDT) Received: from localhost.localdomain ([107.6.117.178]) by mx.google.com with ESMTPSA id oh4sm18428808pdb.42.2015.07.06.06.57.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 06 Jul 2015 06:57:29 -0700 (PDT) From: Jun Nie To: haojian.zhuang@linaro.org, linus.walleij@linaro.org, linux-gpio@vger.kernel.org Cc: tony@atomide.com, shawn.guo@linaro.org, wan.zhijun@zte.com.cn, jason.liu@linaro.org, Jun Nie Subject: [PATCH v2] pinctrl: single: support GPIO for bits pinctrl Date: Mon, 6 Jul 2015 21:57:05 +0800 Message-Id: <1436191025-9024-1-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: linux-gpio-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-gpio@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: jun.nie@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.43 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Support GPIO for one register control multiple pins case with calculating register offset first, then bit offset. Signed-off-by: Jun Nie --- drivers/pinctrl/pinctrl-single.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 13b45f2..4f23ef0 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -494,7 +494,7 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); struct pcs_gpiofunc_range *frange = NULL; struct list_head *pos, *tmp; - int mux_bytes = 0; + int offset, mux_bytes = 0; unsigned data; /* If function mask is null, return directly. */ @@ -507,9 +507,23 @@ static int pcs_request_gpio(struct pinctrl_dev *pctldev, || pin < frange->offset) continue; mux_bytes = pcs->width / BITS_PER_BYTE; - data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; - data |= frange->gpiofunc; - pcs->write(data, pcs->base + pin * mux_bytes); + if (pcs->bits_per_mux) { + int pin_pos, byte_num, num_pins_in_register; + + num_pins_in_register = pcs->width / pcs->bits_per_pin; + byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; + offset = (byte_num / mux_bytes) * mux_bytes; + pin_pos = pin % num_pins_in_register; + pin_pos *= pcs->bits_per_pin; + data = pcs->read(pcs->base + offset) & + ~(pcs->fmask << pin_pos); + data |= (frange->gpiofunc & pcs->fmask) << pin_pos; + } else { + offset = pin * mux_bytes; + data = pcs->read(pcs->base + offset) & ~pcs->fmask; + data |= frange->gpiofunc; + } + pcs->write(data, pcs->base + offset); break; } return 0;