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[209.132.180.67]) by mx.google.com with ESMTP id my7si1235927pbc.191.2014.05.29.08.01.19; Thu, 29 May 2014 08:01:19 -0700 (PDT) Received-SPF: none (google.com: linux-gpio-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757333AbaE2PBO (ORCPT + 1 other); Thu, 29 May 2014 11:01:14 -0400 Received: from mail-wi0-f172.google.com ([209.85.212.172]:50638 "EHLO mail-wi0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756055AbaE2PBN (ORCPT ); Thu, 29 May 2014 11:01:13 -0400 Received: by mail-wi0-f172.google.com with SMTP id hi2so5637436wib.17 for ; Thu, 29 May 2014 08:01:09 -0700 (PDT) X-Received: by 10.180.74.78 with SMTP id r14mr12421167wiv.2.1401375669294; Thu, 29 May 2014 08:01:09 -0700 (PDT) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id p18sm26397113wik.3.2014.05.29.08.01.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 May 2014 08:01:08 -0700 (PDT) From: Linus Walleij To: linux-gpio@vger.kernel.org, David Cohen Cc: Alexandre Courbot , Linus Walleij , "xinhui.pan" Subject: [PATCH] gpio: intel-mid: switch to using gpiolib irqchip helpers Date: Thu, 29 May 2014 17:00:53 +0200 Message-Id: <1401375653-12758-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.9.3 Sender: linux-gpio-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-gpio@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.220.170 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This switches the Intel MID GPIO driver over to using the gpiolib irqchip helpers in the gpiolib core. Cc: David Cohen Cc: xinhui.pan Signed-off-by: Linus Walleij Acked-by: David Cohen --- David can you test this? It's probably easiest for you to just pull in this branch from my GPIO tree and test, because of dependencies: git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git#intel-mid-irqchip-helpers THANKS! --- drivers/gpio/gpio-intel-mid.c | 86 +++++++++++++------------------------------ 1 file changed, 25 insertions(+), 61 deletions(-) diff --git a/drivers/gpio/gpio-intel-mid.c b/drivers/gpio/gpio-intel-mid.c index 118a6bf455d9..aa28c65eb6b4 100644 --- a/drivers/gpio/gpio-intel-mid.c +++ b/drivers/gpio/gpio-intel-mid.c @@ -28,12 +28,10 @@ #include #include #include -#include #include -#include +#include #include #include -#include #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0) #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1) @@ -78,10 +76,12 @@ struct intel_mid_gpio { void __iomem *reg_base; spinlock_t lock; struct pci_dev *pdev; - struct irq_domain *domain; }; -#define to_intel_gpio_priv(chip) container_of(chip, struct intel_mid_gpio, chip) +static inline struct intel_mid_gpio *to_intel_gpio_priv(struct gpio_chip *gc) +{ + return container_of(gc, struct intel_mid_gpio, chip); +} static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, enum GPIO_REG reg_type) @@ -182,15 +182,10 @@ static int intel_gpio_direction_output(struct gpio_chip *chip, return 0; } -static int intel_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -{ - struct intel_mid_gpio *priv = to_intel_gpio_priv(chip); - return irq_create_mapping(priv->domain, offset); -} - static int intel_mid_irq_type(struct irq_data *d, unsigned type) { - struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct intel_mid_gpio *priv = to_intel_gpio_priv(gc); u32 gpio = irqd_to_hwirq(d); unsigned long flags; u32 value; @@ -231,33 +226,11 @@ static void intel_mid_irq_mask(struct irq_data *d) { } -static int intel_mid_irq_reqres(struct irq_data *d) -{ - struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); - - if (gpio_lock_as_irq(&priv->chip, irqd_to_hwirq(d))) { - dev_err(priv->chip.dev, - "unable to lock HW IRQ %lu for IRQ\n", - irqd_to_hwirq(d)); - return -EINVAL; - } - return 0; -} - -static void intel_mid_irq_relres(struct irq_data *d) -{ - struct intel_mid_gpio *priv = irq_data_get_irq_chip_data(d); - - gpio_unlock_as_irq(&priv->chip, irqd_to_hwirq(d)); -} - static struct irq_chip intel_mid_irqchip = { .name = "INTEL_MID-GPIO", .irq_mask = intel_mid_irq_mask, .irq_unmask = intel_mid_irq_unmask, .irq_set_type = intel_mid_irq_type, - .irq_request_resources = intel_mid_irq_reqres, - .irq_release_resources = intel_mid_irq_relres, }; static const struct intel_mid_gpio_ddata gpio_lincroft = { @@ -330,8 +303,9 @@ MODULE_DEVICE_TABLE(pci, intel_gpio_ids); static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc) { + struct gpio_chip *gc = irq_desc_get_handler_data(desc); + struct intel_mid_gpio *priv = to_intel_gpio_priv(gc); struct irq_data *data = irq_desc_get_irq_data(desc); - struct intel_mid_gpio *priv = irq_data_get_irq_handler_data(data); struct irq_chip *chip = irq_data_get_irq_chip(data); u32 base, gpio, mask; unsigned long pending; @@ -345,7 +319,7 @@ static void intel_mid_irq_handler(unsigned irq, struct irq_desc *desc) mask = BIT(gpio); /* Clear before handling so we can't lose an edge */ writel(mask, gedr); - generic_handle_irq(irq_find_mapping(priv->domain, + generic_handle_irq(irq_find_mapping(gc->irqdomain, base + gpio)); } } @@ -371,23 +345,6 @@ static void intel_mid_irq_init_hw(struct intel_mid_gpio *priv) } } -static int intel_gpio_irq_map(struct irq_domain *d, unsigned int irq, - irq_hw_number_t hwirq) -{ - struct intel_mid_gpio *priv = d->host_data; - - irq_set_chip_and_handler(irq, &intel_mid_irqchip, handle_simple_irq); - irq_set_chip_data(irq, priv); - irq_set_irq_type(irq, IRQ_TYPE_NONE); - - return 0; -} - -static const struct irq_domain_ops intel_gpio_irq_ops = { - .map = intel_gpio_irq_map, - .xlate = irq_domain_xlate_twocell, -}; - static int intel_gpio_runtime_idle(struct device *dev) { int err = pm_schedule_suspend(dev, 500); @@ -441,7 +398,6 @@ static int intel_gpio_probe(struct pci_dev *pdev, priv->chip.direction_output = intel_gpio_direction_output; priv->chip.get = intel_gpio_get; priv->chip.set = intel_gpio_set; - priv->chip.to_irq = intel_gpio_to_irq; priv->chip.base = gpio_base; priv->chip.ngpio = ddata->ngpio; priv->chip.can_sleep = false; @@ -449,11 +405,6 @@ static int intel_gpio_probe(struct pci_dev *pdev, spin_lock_init(&priv->lock); - priv->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio, - irq_base, &intel_gpio_irq_ops, priv); - if (!priv->domain) - return -ENOMEM; - pci_set_drvdata(pdev, priv); retval = gpiochip_add(&priv->chip); if (retval) { @@ -461,10 +412,23 @@ static int intel_gpio_probe(struct pci_dev *pdev, return retval; } + retval = gpiochip_irqchip_add(&priv->chip, + &intel_mid_irqchip, + irq_base, + handle_simple_irq, + IRQ_TYPE_NONE); + if (retval) { + dev_err(&pdev->dev, + "could not connect irqchip to gpiochip\n"); + return retval; + } + intel_mid_irq_init_hw(priv); - irq_set_handler_data(pdev->irq, priv); - irq_set_chained_handler(pdev->irq, intel_mid_irq_handler); + gpiochip_set_chained_irqchip(&priv->chip, + &intel_mid_irqchip, + pdev->irq, + intel_mid_irq_handler); pm_runtime_put_noidle(&pdev->dev); pm_runtime_allow(&pdev->dev);