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[209.132.180.67]) by mx.google.com with ESMTP id ai4si17199680pbd.340.2014.04.21.18.36.03; Mon, 21 Apr 2014 18:36:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751398AbaDVBgC (ORCPT + 9 others); Mon, 21 Apr 2014 21:36:02 -0400 Received: from mail-pa0-f48.google.com ([209.85.220.48]:42326 "EHLO mail-pa0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751280AbaDVBgB (ORCPT ); Mon, 21 Apr 2014 21:36:01 -0400 Received: by mail-pa0-f48.google.com with SMTP id hz1so4325825pad.21 for ; Mon, 21 Apr 2014 18:36:00 -0700 (PDT) X-Received: by 10.68.178.162 with SMTP id cz2mr41014424pbc.51.1398130560674; Mon, 21 Apr 2014 18:36:00 -0700 (PDT) Received: from localhost.localdomain ([140.206.182.114]) by mx.google.com with ESMTPSA id my6sm80935421pbc.36.2014.04.21.18.35.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 21 Apr 2014 18:35:59 -0700 (PDT) From: Haojian Zhuang To: xuwei5@hisilicon.com, linus.walleij@linaro.org, grant.likely@linaro.org, robh+dt@kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, baruch@tkos.co.il Cc: Haojian Zhuang Subject: [PATCH 1/2] gpio: pl061: get gpio base from alias id Date: Tue, 22 Apr 2014 09:35:42 +0800 Message-Id: <1398130543-19454-1-git-send-email-haojian.zhuang@linaro.org> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: devicetree@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: haojian.zhuang@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , If gpio base number isn't specified, the gpio base will be find from the end of gpio number. In order to keep with schematics, use alias to get the ID of gpio chip. Signed-off-by: Haojian Zhuang --- .../devicetree/bindings/gpio/gpio-pl061.txt | 31 ++++++++++++++++++++++ drivers/gpio/gpio-pl061.c | 14 +++++++++- 2 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/gpio/gpio-pl061.txt diff --git a/Documentation/devicetree/bindings/gpio/gpio-pl061.txt b/Documentation/devicetree/bindings/gpio/gpio-pl061.txt new file mode 100644 index 0000000..164b5ba --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-pl061.txt @@ -0,0 +1,31 @@ +PL061 GPIO controller bindings + +Required properties: +- compatible: + - "arm,pl061", "arm,primecell". +- #gpio-cells : Should be two. + - first cell is the gpio pin number + - second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low +- gpio-controller : Marks the device node as a GPIO controller. +- interrupt-controller : Marks the device node as an interrupt controller. +- #interrupt-cells : Should be two. + - first cell is the hw irq number + - second cell is used to specify the interrupt type: + 0 = default, unspecified type + 1 = rising edge triggered + 2 = falling edge triggered + 4 = high level triggered + 8 = low level triggered + +Example: + gpio0: gpio@fc806000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xfc806000 0x1000>; + interrupts = <0 64 0x4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index b0f4752..14f3ab5 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -236,6 +236,18 @@ static struct irq_chip pl061_irqchip = { .irq_set_type = pl061_irq_type, }; +/* Parse gpio base from DT */ +static int pl061_parse_gpio_base(struct device *dev) +{ + struct device_node *np = dev->of_node; + int ret, id; + + id = of_alias_get_id(np, "gpio"); + if (id < 0) + return id; + return (id * PL061_GPIO_NR); +} + static int pl061_probe(struct amba_device *adev, const struct amba_id *id) { struct device *dev = &adev->dev; @@ -255,7 +267,7 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id) return -ENODEV; } } else { - chip->gc.base = -1; + chip->gc.base = pl061_parse_gpio_base(dev); irq_base = 0; }