From patchwork Tue Nov 26 13:23:58 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 21778 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qa0-f70.google.com (mail-qa0-f70.google.com [209.85.216.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 58497202E0 for ; Tue, 26 Nov 2013 13:24:06 +0000 (UTC) Received: by mail-qa0-f70.google.com with SMTP id j5sf20277892qaq.9 for ; Tue, 26 Nov 2013 05:24:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:x-original-sender:x-original-authentication-results :precedence:mailing-list:list-id:list-post:list-help:list-archive :list-unsubscribe; bh=bD1ZnHKjitOccVDSc4rb7kPdzXSgVKTyHXkZoiL1DSE=; b=W4lG0gMIP6lyhiLmoU+StuXxQ7OfTicn+8t8yivdXABPZDJWjHxjoqwS4dwmTOxodZ D05DMPR87fDUrPaCv/5gLPmwDpZTAnfWgoKKN8Wjm4p2Nt8rQV5XlVp02zscLBgixyeO fy14pMF1JNSiTgQy+UsRPeUL+hSA/7OmmtY3cXGU2Rse6yU6qZWSWur/cz/2hTvHsmV0 RQlA9ULLn1i0C0TYMKKa6GZBTOnlijwK7uuIEOTmRAtn+vYsUSWP/dgypZcPEDLd9AhU 4PbYAJcd0VYBYtdDy03QqE0xX7Y+siWynwyxUkMO2d21WYe7KVIVLulzf5/nqFnn/og0 diPg== X-Gm-Message-State: ALoCoQmDiVasUfCrgG6CXK5iufbDfnwj9B3jnjUZV/NX6TP9w3yw6z2/0CivfiDn4ZNLb1g/hAEl X-Received: by 10.58.112.195 with SMTP id is3mr11231095veb.29.1385472245535; Tue, 26 Nov 2013 05:24:05 -0800 (PST) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.2.69 with SMTP id 5ls2663107qes.98.gmail; Tue, 26 Nov 2013 05:24:05 -0800 (PST) X-Received: by 10.221.64.17 with SMTP id xg17mr30424256vcb.5.1385472245477; Tue, 26 Nov 2013 05:24:05 -0800 (PST) Received: from mail-vb0-f42.google.com (mail-vb0-f42.google.com [209.85.212.42]) by mx.google.com with ESMTPS id fx15si19517040vec.72.2013.11.26.05.24.05 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 26 Nov 2013 05:24:05 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.42; Received: by mail-vb0-f42.google.com with SMTP id w18so3996788vbj.1 for ; Tue, 26 Nov 2013 05:24:05 -0800 (PST) X-Received: by 10.220.169.203 with SMTP id a11mr5190461vcz.26.1385472245395; Tue, 26 Nov 2013 05:24:05 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp212256vcz; Tue, 26 Nov 2013 05:24:04 -0800 (PST) X-Received: by 10.152.20.6 with SMTP id j6mr25790278lae.8.1385472244376; Tue, 26 Nov 2013 05:24:04 -0800 (PST) Received: from mail-lb0-f174.google.com (mail-lb0-f174.google.com [209.85.217.174]) by mx.google.com with ESMTPS id rc10si5089742lbb.14.2013.11.26.05.24.03 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 26 Nov 2013 05:24:04 -0800 (PST) Received-SPF: neutral (google.com: 209.85.217.174 is neither permitted nor denied by best guess record for domain of linus.walleij@linaro.org) client-ip=209.85.217.174; Received: by mail-lb0-f174.google.com with SMTP id c11so4344553lbj.19 for ; Tue, 26 Nov 2013 05:24:03 -0800 (PST) X-Received: by 10.112.210.66 with SMTP id ms2mr354554lbc.51.1385472243756; Tue, 26 Nov 2013 05:24:03 -0800 (PST) Received: from localhost.localdomain ([85.235.11.236]) by mx.google.com with ESMTPSA id c15sm4136966lbq.11.2013.11.26.05.24.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Nov 2013 05:24:02 -0800 (PST) From: Linus Walleij To: linux-gpio@vger.kernel.org Cc: Alexandre Courbot , Linus Walleij , Haojian Zhuang , Baruch Siach , Deepak Sikri Subject: [PATCH 2/3] gpio: pl061: refactor type setting Date: Tue, 26 Nov 2013 14:23:58 +0100 Message-Id: <1385472238-26001-1-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 1.8.3.1 X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: linus.walleij@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.42 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Refactor this function so that I can understand it, do one big read/modify/write operation and have the bitmask in a variable instead of recalculating it every time it's needed. Cc: Haojian Zhuang Cc: Baruch Siach Cc: Deepak Sikri Signed-off-by: Linus Walleij --- drivers/gpio/gpio-pl061.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index 1c37c97acc76..c3935c58185d 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -150,6 +150,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) int offset = irqd_to_hwirq(d); unsigned long flags; u8 gpiois, gpioibe, gpioiev; + u8 bit = BIT(offset); if (offset < 0 || offset >= PL061_GPIO_NR) return -EINVAL; @@ -157,30 +158,31 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) spin_lock_irqsave(&chip->lock, flags); gpioiev = readb(chip->base + GPIOIEV); - gpiois = readb(chip->base + GPIOIS); + gpioibe = readb(chip->base + GPIOIBE); + if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { - gpiois |= 1 << offset; + gpiois |= bit; if (trigger & IRQ_TYPE_LEVEL_HIGH) - gpioiev |= 1 << offset; + gpioiev |= bit; else - gpioiev &= ~(1 << offset); + gpioiev &= ~bit; } else - gpiois &= ~(1 << offset); - writeb(gpiois, chip->base + GPIOIS); + gpiois &= ~bit; - gpioibe = readb(chip->base + GPIOIBE); if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) - gpioibe |= 1 << offset; + /* Setting this makes GPIOEV be ignored */ + gpioibe |= bit; else { - gpioibe &= ~(1 << offset); + gpioibe &= ~bit; if (trigger & IRQ_TYPE_EDGE_RISING) - gpioiev |= 1 << offset; + gpioiev |= bit; else if (trigger & IRQ_TYPE_EDGE_FALLING) - gpioiev &= ~(1 << offset); + gpioiev &= ~bit; } - writeb(gpioibe, chip->base + GPIOIBE); + writeb(gpiois, chip->base + GPIOIS); + writeb(gpioibe, chip->base + GPIOIBE); writeb(gpioiev, chip->base + GPIOIEV); spin_unlock_irqrestore(&chip->lock, flags);