| Message ID | cover.1625064076.git.geert+renesas@glider.be |
|---|---|
| Headers | show |
| Series | pinctrl: renesas: Add r8a77995 bias pinconf support | expand |
Hi Geert, On 2021-06-30 16:50:42 +0200, Geert Uytterhoeven wrote: > When disabling pin bias, there is no need to touch the LSI pin > pull-up/down control register (PUDn), which selects between pull-up and > pull-down. Just disabling the pull-up/down function through the LSI pin > pull-enable register (PUENn) us sufficient. s/us/is/ > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> > --- > v2: > - New. > --- > drivers/pinctrl/renesas/pinctrl.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c > index bb488af298623407..85cb78cfcfa6c37d 100644 > --- a/drivers/pinctrl/renesas/pinctrl.c > +++ b/drivers/pinctrl/renesas/pinctrl.c > @@ -898,17 +898,17 @@ void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, > > if (reg->puen) { > enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit); > - if (bias != PIN_CONFIG_BIAS_DISABLE) > + if (bias != PIN_CONFIG_BIAS_DISABLE) { > enable |= BIT(bit); > > - if (reg->pud) { > - updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); > - if (bias == PIN_CONFIG_BIAS_PULL_UP) > - updown |= BIT(bit); > + if (reg->pud) { > + updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); > + if (bias == PIN_CONFIG_BIAS_PULL_UP) > + updown |= BIT(bit); > > - sh_pfc_write(pfc, reg->pud, updown); > + sh_pfc_write(pfc, reg->pud, updown); > + } > } > - > sh_pfc_write(pfc, reg->puen, enable); > } else { > enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit); > -- > 2.25.1 >
Hi all, This patch series adds a small optimization to R-Car pin bias handling, and adds bias pinconf support for the R-Car D3 SoC. Changes compared to v1[1]: - Drop all accepted patches, - Add [PATCH v2 1/2], - Add Reviewed-by, - Fix NFRE# and NFWE# handling, now we received confirmation that the documentation is correct. The first patch has been tested on Koelsch and Salvator-XS. The second patch has been tested on a remote Draak development board by specifying one of the "bias-{pull-{down,enable},disable}" properties for the "GP_3_0" and "GP_3_1" pins from DT, and inspecting the impact on the PUEN2 and PUD2 registers. Due to the remote setup, actual voltage levels could not be measured. Note that enabling pull-down for "GP_3_0" breaks eMMC operation, as this pin is used as the eMMC's "CMD" signal. I plan to queue this in renesas-pinctrl for v5.15. Thanks for your comments! [1] [PATCH 00/12] pinctrl: renesas: Add more bias pinconf support https://lore.kernel.org/linux-renesas-soc/cover.1619785375.git.geert+renesas@glider.be/ Geert Uytterhoeven (2): pinctrl: renesas: rcar: Avoid changing PUDn when disabling bias pinctrl: renesas: r8a77995: Add bias pinconf support drivers/pinctrl/renesas/pfc-r8a77995.c | 320 ++++++++++++++++++++++++- drivers/pinctrl/renesas/pinctrl.c | 16 +- drivers/pinctrl/renesas/sh_pfc.h | 3 + 3 files changed, 323 insertions(+), 16 deletions(-)