| Message ID | IA1PR20MB49535F9918829FA524BDB02ABBA82@IA1PR20MB4953.namprd20.prod.outlook.com |
|---|---|
| Headers | show |
| Series | riscv: sophgo: Add pinctrl support for CV1800 series SoC | expand |
On Mon, Jul 22, 2024 at 09:39:20AM +0800, Inochi Amaoto wrote: > Add pinctrl support for Sophgo CV1800 series SoC. > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > --- > .../pinctrl/sophgo,cv1800-pinctrl.yaml | 129 ++++++++++++++++++ > include/dt-bindings/pinctrl/pinctrl-cv1800b.h | 63 +++++++++ > include/dt-bindings/pinctrl/pinctrl-cv1812h.h | 127 +++++++++++++++++ > include/dt-bindings/pinctrl/pinctrl-cv18xx.h | 19 +++ > include/dt-bindings/pinctrl/pinctrl-sg2000.h | 127 +++++++++++++++++ > include/dt-bindings/pinctrl/pinctrl-sg2002.h | 79 +++++++++++ > 6 files changed, 544 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml > create mode 100644 include/dt-bindings/pinctrl/pinctrl-cv1800b.h > create mode 100644 include/dt-bindings/pinctrl/pinctrl-cv1812h.h > create mode 100644 include/dt-bindings/pinctrl/pinctrl-cv18xx.h > create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2000.h > create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2002.h > > diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml > new file mode 100644 > index 000000000000..e6bd271ad22d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml > @@ -0,0 +1,129 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Sophgo CV1800 Pin Controller > + > +maintainers: > + - Inochi Amaoto <inochiama@outlook.com> > + > +properties: > + compatible: > + enum: > + - sophgo,cv1800b-pinctrl > + - sophgo,cv1812h-pinctrl > + - sophgo,sg2000-pinctrl > + - sophgo,sg2002-pinctrl > + > + reg: > + items: > + - description: pinctrl for system domain > + - description: pinctrl for rtc domain > + > + reg-names: > + items: > + - const: sys > + - const: rtc > + > + resets: > + maxItems: 1 > + > +patternProperties: > + '-cfg$': > + type: object > + description: | Don't need '|' if no formatting. > + A pinctrl node should contain at least one subnode representing the > + pinctrl groups available on the machine. > + > + additionalProperties: false > + > + patternProperties: > + '-pins$': > + type: object > + description: | > + Each subnode will list the pins it needs, and how they should > + be configured, with regard to muxer configuration, bias, input > + enable/disable, input schmitt trigger, slew-rate, drive strength > + and bus hold state. In addition, all pins in the same subnode > + should have the same power domain. For configuration detail, > + refer to https://github.com/sophgo/sophgo-doc/. > + $ref: /schemas/pinctrl/pincfg-node.yaml > + > + properties: > + pinmux: > + description: | > + The list of GPIOs and their mux settings that properties in the > + node apply to. This should be set using the GPIOMUX or GPIOMUX2 > + macro. > + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux You already referenced this above which is the right way. Drop this $ref. > + > + bias-pull-up: > + type: boolean > + > + bias-pull-down: > + type: boolean > + > + drive-strength: > + description: typical current when output high level, but in mA. > + $ref: /schemas/types.yaml#/definitions/uint32 > + > + drive-strength-microamp: > + description: typical current when output high level. New binding, why do you need both of these properties? Use the latter. > + > + input-schmitt-microvolt: > + description: typical threshold for schmitt trigger. No constraints? > + > + power-source: > + description: power supplies at X mV. > + enum: [ 1800, 3300 ] > + > + slew-rate: > + description: slew rate for output buffer (0 is fast, 1 is slow) > + enum: [ 0, 1 ] > + > + bias-bus-hold: > + type: boolean > + > + required: > + - pinmux > + - power-source > + > + additionalProperties: false > + > +required: > + - compatible > + - reg > + - reg-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/pinctrl/pinctrl-cv1800b.h> > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; You can remove 'soc' node from the example. 1 cell is the default for examples. > + > + pinctrl@3001000 { > + compatible = "sophgo,cv1800b-pinctrl"; > + reg = <0x03001000 0x1000>, > + <0x05027000 0x1000>; > + reg-names = "sys", "rtc"; > + > + uart0_cfg: uart0-cfg { > + uart0-pins { > + pinmux = <PINMUX(PIN_UART0_TX, 0)>, > + <PINMUX(PIN_UART0_RX, 0)>; > + bias-pull-up; > + drive-strength = <2>; > + power-source = <3300>; > + slew-rate = <0>; > + }; > + }; > + }; > + }; > + > +...
On Tue, Jul 23, 2024 at 01:31:53PM GMT, Rob Herring wrote: > On Mon, Jul 22, 2024 at 09:39:20AM +0800, Inochi Amaoto wrote: > > Add pinctrl support for Sophgo CV1800 series SoC. > > > > Signed-off-by: Inochi Amaoto <inochiama@outlook.com> > > --- > > .../pinctrl/sophgo,cv1800-pinctrl.yaml | 129 ++++++++++++++++++ > > include/dt-bindings/pinctrl/pinctrl-cv1800b.h | 63 +++++++++ > > include/dt-bindings/pinctrl/pinctrl-cv1812h.h | 127 +++++++++++++++++ > > include/dt-bindings/pinctrl/pinctrl-cv18xx.h | 19 +++ > > include/dt-bindings/pinctrl/pinctrl-sg2000.h | 127 +++++++++++++++++ > > include/dt-bindings/pinctrl/pinctrl-sg2002.h | 79 +++++++++++ > > 6 files changed, 544 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml > > create mode 100644 include/dt-bindings/pinctrl/pinctrl-cv1800b.h > > create mode 100644 include/dt-bindings/pinctrl/pinctrl-cv1812h.h > > create mode 100644 include/dt-bindings/pinctrl/pinctrl-cv18xx.h > > create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2000.h > > create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2002.h > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml > > new file mode 100644 > > index 000000000000..e6bd271ad22d > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/sophgo,cv1800-pinctrl.yaml > > @@ -0,0 +1,129 @@ > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/sophgo,cv1800-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Sophgo CV1800 Pin Controller > > + > > +maintainers: > > + - Inochi Amaoto <inochiama@outlook.com> > > + > > +properties: > > + compatible: > > + enum: > > + - sophgo,cv1800b-pinctrl > > + - sophgo,cv1812h-pinctrl > > + - sophgo,sg2000-pinctrl > > + - sophgo,sg2002-pinctrl > > + > > + reg: > > + items: > > + - description: pinctrl for system domain > > + - description: pinctrl for rtc domain > > + > > + reg-names: > > + items: > > + - const: sys > > + - const: rtc > > + > > + resets: > > + maxItems: 1 > > + > > +patternProperties: > > + '-cfg$': > > + type: object > > + description: | > > Don't need '|' if no formatting. > > > + A pinctrl node should contain at least one subnode representing the > > + pinctrl groups available on the machine. > > + > > + additionalProperties: false > > + > > + patternProperties: > > + '-pins$': > > + type: object > > + description: | > > + Each subnode will list the pins it needs, and how they should > > + be configured, with regard to muxer configuration, bias, input > > + enable/disable, input schmitt trigger, slew-rate, drive strength > > + and bus hold state. In addition, all pins in the same subnode > > + should have the same power domain. For configuration detail, > > + refer to https://github.com/sophgo/sophgo-doc/. > > + $ref: /schemas/pinctrl/pincfg-node.yaml > > + > > + properties: > > + pinmux: > > + description: | > > + The list of GPIOs and their mux settings that properties in the > > + node apply to. This should be set using the GPIOMUX or GPIOMUX2 > > + macro. > > + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pinmux > > You already referenced this above which is the right way. Drop this > $ref. > > > + > > + bias-pull-up: > > + type: boolean > > + > > + bias-pull-down: > > + type: boolean > > + > > + drive-strength: > > + description: typical current when output high level, but in mA. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + drive-strength-microamp: > > + description: typical current when output high level. > > New binding, why do you need both of these properties? Use the latter. > > > + > > + input-schmitt-microvolt: > > + description: typical threshold for schmitt trigger. > > No constraints? > Since the value of the pin depends on the pin type and attribute "power-source", it is too hard to give accurate constraint for the binding. So I left the check in the driver. Although it is possible to give a maximum to fit all the pins, but I think it is kind of meaningless. > > + > > + power-source: > > + description: power supplies at X mV. > > + enum: [ 1800, 3300 ] > > + > > + slew-rate: > > + description: slew rate for output buffer (0 is fast, 1 is slow) > > + enum: [ 0, 1 ] > > + > > + bias-bus-hold: > > + type: boolean > > + > > + required: > > + - pinmux > > + - power-source > > + > > + additionalProperties: false > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/pinctrl/pinctrl-cv1800b.h> > > + > > + soc { > > + #address-cells = <1>; > > + #size-cells = <1>; > > You can remove 'soc' node from the example. 1 cell is the default for > examples. > > > + > > + pinctrl@3001000 { > > + compatible = "sophgo,cv1800b-pinctrl"; > > + reg = <0x03001000 0x1000>, > > + <0x05027000 0x1000>; > > + reg-names = "sys", "rtc"; > > + > > + uart0_cfg: uart0-cfg { > > + uart0-pins { > > + pinmux = <PINMUX(PIN_UART0_TX, 0)>, > > + <PINMUX(PIN_UART0_RX, 0)>; > > + bias-pull-up; > > + drive-strength = <2>; > > + power-source = <3300>; > > + slew-rate = <0>; > > + }; > > + }; > > + }; > > + }; > > + > > +...