From patchwork Fri Sep 13 07:43:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Billy Tsai X-Patchwork-Id: 828728 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C87D61BDAB2; Fri, 13 Sep 2024 07:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726213420; cv=none; b=lK0lc/S+ngfZJVouiMl62P1mRBuPZ6HPh7Khog166euAXMpIcrLJKAyX/YY78K17M5XlhRS2/EnzAdlZH1s3ykAcPEHKa07bSb6Hk74kWe6cCrEtGyHO2u6WurrYn2Oa6GH6kf7rWfgGLDBSDuCCZ2LoFpGNhj5erizzqwN6lIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1726213420; c=relaxed/simple; bh=L4uQfDONVw2EilB+3eyY/Qj18I0ieYrCqIDqrOFePiw=; h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type; b=Eekbcg2/G6K57JfssNZ8tDDl9F+g+Wn4kgL9R9CD9VyUw6Cbjciodk6q1fhmdIVeDP5NyavOQaw5bSSP+m2mqVXg3142F6rU36U4ZNtO690FzQoXORl9NrRu+5lv3R2Pz+D1LgtEebHsoKcgV3GAbbOyRZaDEQ9ZycG1d6NfH1U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Fri, 13 Sep 2024 15:43:25 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Fri, 13 Sep 2024 15:43:25 +0800 From: Billy Tsai To: , , , , , , , , , , , , , Subject: [PATCH v3 0/6] Add Aspeed G7 gpio support Date: Fri, 13 Sep 2024 15:43:19 +0800 Message-ID: <20240913074325.239390-1-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Aspeed 7th generation SoC features two GPIO controllers: one with 12 GPIO pins and another with 216 GPIO pins. The main difference from the previous generation is that the control logic has been updated to support per-pin control, allowing each pin to have its own 32-bit register for configuring value, direction, interrupt type, and more. This patch serial also add low-level operations (llops) to abstract the register access for GPIO registers and the coprocessor request/release in gpio-aspeed.c making it easier to extend the driver to support different hardware register layouts. Change since v2: - Correct minItems for gpio-line names - Remove the example for ast2700, because it’s the same as the AST2600 - Fix the sparse warning which is reported by the test robot - Remove the version and use the match data to replace it. - Add another two patches one for deferred probe one for flush write. Changes since v1: - Merge the gpio-aspeed-g7.c into the gpio-aspeed.c. - Create the llops in gpio-aspeed.c for flexibility. Billy Tsai (6): dt-bindings: gpio: aspeed,ast2400-gpio: Support ast2700 gpio: aspeed: Remove the name for bank array gpio: aspeed: Create llops to handle hardware access gpio: aspeed: Support G7 Aspeed gpio controller gpio: aspeed: Change the macro to support deferred probe gpio: aspeed: Add the flush write to ensure the write complete. .../bindings/gpio/aspeed,ast2400-gpio.yaml | 19 +- drivers/gpio/gpio-aspeed.c | 498 +++++++++++------- 2 files changed, 313 insertions(+), 204 deletions(-)