| Message ID | 20240807082843.352937-1-ivo.ivanov.ivanov1@gmail.com |
|---|---|
| Headers | show |
| Series | Add minimal Exynos8895 SoC and SM-G950F support | expand |
Unfortunately, it turned out that I have an issue with my git configuration. I'm sorry for the inconvenience, I'll resend a V2 without the sendemail.from. On 8/7/24 11:28, ivo.ivanov.ivanov1@gmail.com wrote: > From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > > Hi folks, > > This series adds initial SoC support for the Exynos 8895 SoC and also > initial board support for Samsung Galaxy S8 phone (SM-G950F), codenamed > dreamlte. > > The Exynos 8895 SoC is also used in S8 Plus (dream2lte), Note 8 (greatlte) > and Meizu 15 Plus (m1891). Currently DT is added for the Exynos 8895 SoC > and dreamlte, but it should be really easy to adapt for the other devices > with the same SoC. > > The support added in this series consists of: > * cpus > * pinctrl > * gpio > * simple-framebuffer > * pstore > > This is enough to reach a minimal initramfs shell using an upstream kernel. > More platform support will be added in the future. > > The preferred way to boot this device is by using a small shim bl called > uniLoader [1], which packages the mainline kernel and DT and jumps to > the kernel. This is done in order to work around some issues caused by > the stock, and non-replacable Samsung S-Boot bootloader. For example, > S-Boot leaves the decon trigger control unset, which causes the framebuffer > to not refresh. > > [1] https://github.com/ivoszbg/uniLoader > > Kind regards, > > Ivaylo. > > Ivaylo Ivanov (10): > dt-bindings: arm: cpus: Add Samsung Mongoose M2 > dt-bindings: hwinfo: samsung,exynos-chipid: add exynos8895 compatible > soc: samsung: exynos-chipid: add exynos8895 SoC support > dt-bindings: pinctrl: samsung: Add compatible for Exynos8895 SoC > pinctrl: samsung: Add exynos8895 SoC pinctrl configuration > dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible > dt-bindings: soc: samsung: exynos-pmu: Add exynos8895 compatible > arm64: dts: exynos: Add initial support for exynos8895 SoC > dt-bindings: arm: samsung: Document dreamlte board binding > arm64: dts: exynos: Add initial support for Samsung Galaxy S8 > > .../devicetree/bindings/arm/cpus.yaml | 1 + > .../bindings/arm/samsung/samsung-boards.yaml | 6 + > .../hwinfo/samsung,exynos-chipid.yaml | 1 + > .../samsung,pinctrl-wakeup-interrupt.yaml | 1 + > .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + > .../bindings/soc/samsung/exynos-pmu.yaml | 1 + > arch/arm64/boot/dts/exynos/Makefile | 1 + > .../boot/dts/exynos/exynos8895-dreamlte.dts | 126 ++ > .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ > arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ > .../pinctrl/samsung/pinctrl-exynos-arm64.c | 137 ++ > drivers/pinctrl/samsung/pinctrl-exynos.h | 10 + > drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + > drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + > drivers/soc/samsung/exynos-chipid.c | 1 + > 15 files changed, 1920 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts > create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi >
On 07/08/2024 11:06, Ivaylo Ivanov wrote: > Unfortunately, it turned out that I have an issue with my git > > configuration. I'm sorry for the inconvenience, I'll resend a V2 > > without the sendemail.from. > "From" header is not a problem. It's ok. Did you mean something else? Best regards, Krzysztof
Well, thanks, I meant the "From" header. Although right as you replied, I sent the v2 :P. I'll just wait out for the review notes and send a following v3. My bad. Best regards, and thanks again, Ivaylo On 8/7/24 12:09, Krzysztof Kozlowski wrote: > On 07/08/2024 11:06, Ivaylo Ivanov wrote: >> Unfortunately, it turned out that I have an issue with my git >> >> configuration. I'm sorry for the inconvenience, I'll resend a V2 >> >> without the sendemail.from. >> > "From" header is not a problem. It's ok. Did you mean something else? > > Best regards, > Krzysztof >
On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com wrote: > From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > > Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy > S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu > 15 Plus (m1891). Add minimal support for that SoC, including: > > - All 8 cores via PSCI > - ChipID > - Generic ARMV8 Timer > - Enumarate all pinctrl nodes > > Further platform support will be added over time. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ > arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ > 2 files changed, 1631 insertions(+) > create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi > create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi > > diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi > new file mode 100644 > index 000000000..1dcb61e2e > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi > @@ -0,0 +1,1378 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source > + * > + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include "exynos-pinctrl.h" > + > +&pinctrl_alive { > + gpa0: gpa0 { I do not believe this was tested. See maintainer SoC profile for Samsung Exynos. Limited review follows due to lack of testing. > +}; > diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi > new file mode 100644 > index 000000000..3ed381ee5 > --- /dev/null > +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi > @@ -0,0 +1,253 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Samsung's Exynos 8895 SoC device tree source > + * > + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + compatible = "samsung,exynos8895"; > + #address-cells = <2>; > + #size-cells = <1>; > + > + interrupt-parent = <&gic>; > + > + aliases { > + pinctrl0 = &pinctrl_alive; > + pinctrl1 = &pinctrl_abox; > + pinctrl2 = &pinctrl_vts; > + pinctrl3 = &pinctrl_fsys0; > + pinctrl4 = &pinctrl_fsys1; > + pinctrl5 = &pinctrl_busc; > + pinctrl6 = &pinctrl_peric0; > + pinctrl7 = &pinctrl_peric1; > + }; > + > + arm-a53-pmu { Are there two pmus? > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-affinity = <&cpu0>, > + <&cpu1>, > + <&cpu2>, > + <&cpu3>, > + <&cpu4>, > + <&cpu5>, > + <&cpu6>, > + <&cpu7>; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x100>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x101>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x102>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x103>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu@0 { > + device_type = "cpu"; > + compatible = "samsung,mongoose-m2"; > + reg = <0x0>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@1 { > + device_type = "cpu"; > + compatible = "samsung,mongoose-m2"; > + reg = <0x1>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@2 { > + device_type = "cpu"; > + compatible = "samsung,mongoose-m2"; > + reg = <0x2>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@3 { > + device_type = "cpu"; > + compatible = "samsung,mongoose-m2"; > + reg = <0x3>; > + enable-method = "psci"; > + }; > + }; > + > + psci { > + compatible = "arm,psci"; > + method = "smc"; > + cpu_suspend = <0xc4000001>; > + cpu_off = <0x84000002>; > + cpu_on = <0xc4000003>; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + clock-frequency = <26000000>; Hm? I think this was explicitly disallowed. > + }; > + > + fixed-rate-clocks { Keep order of properties, just like DTS coding style asks. Anyway, fixed-rate-clocks wrapper is not needed, drop. > + oscclk: osc-clock { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-output-names = "oscclk"; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0x0 0x0 0x0 0x20000000>; > + > + chipid@10000000 { > + compatible = "samsung,exynos8895-chipid", > + "samsung,exynos850-chipid"; > + reg = <0x10000000 0x24>; > + }; > + > + gic: interrupt-controller@10200000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + #address-cells = <0>; > + interrupt-controller; > + reg = <0x10201000 0x1000>, > + <0x10202000 0x1000>, > + <0x10204000 0x2000>, > + <0x10206000 0x2000>; > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | > + IRQ_TYPE_LEVEL_HIGH)>; > + }; > + > + pinctrl_alive: pinctrl@164b0000 { > + compatible = "samsung,exynos8895-pinctrl"; > + reg = <0x164b0000 0x1000>; > + > + wakeup-interrupt-controller { > + compatible = "samsung,exynos8895-wakeup-eint", > + "samsung,exynos7-wakeup-eint"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + pinctrl_abox: pinctrl@13e60000 { This does not look ordered. See DTS coding style. Best regards, Krzysztof
On 8/7/24 12:20, Krzysztof Kozlowski wrote: > On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com wrote: >> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> >> Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy >> S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu >> 15 Plus (m1891). Add minimal support for that SoC, including: >> >> - All 8 cores via PSCI >> - ChipID >> - Generic ARMV8 Timer >> - Enumarate all pinctrl nodes >> >> Further platform support will be added over time. >> >> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> --- >> .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ >> arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ >> 2 files changed, 1631 insertions(+) >> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi >> >> diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >> new file mode 100644 >> index 000000000..1dcb61e2e >> --- /dev/null >> +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >> @@ -0,0 +1,1378 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source >> + * >> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include "exynos-pinctrl.h" >> + >> +&pinctrl_alive { >> + gpa0: gpa0 { > I do not believe this was tested. See maintainer SoC profile for Samsung > Exynos. > > Limited review follows due to lack of testing. > > >> +}; >> diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi >> new file mode 100644 >> index 000000000..3ed381ee5 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi >> @@ -0,0 +1,253 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Samsung's Exynos 8895 SoC device tree source >> + * >> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> + */ >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + compatible = "samsung,exynos8895"; >> + #address-cells = <2>; >> + #size-cells = <1>; >> + >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + pinctrl0 = &pinctrl_alive; >> + pinctrl1 = &pinctrl_abox; >> + pinctrl2 = &pinctrl_vts; >> + pinctrl3 = &pinctrl_fsys0; >> + pinctrl4 = &pinctrl_fsys1; >> + pinctrl5 = &pinctrl_busc; >> + pinctrl6 = &pinctrl_peric0; >> + pinctrl7 = &pinctrl_peric1; >> + }; >> + >> + arm-a53-pmu { > Are there two pmus? Hm. The Downstream kernel has them all under one node with compatible 'arm,armv8-pmuv3', same as with Exynos 7885. So it should have two PMUs, one for each cluster. Considering the second cluster consists of Samsung's custom Mongoose M2 cores, what would be the most adequate thing to do? Keep the first PMU as "arm,cortex-a53-pmu" and use the SW model "arm,armv8-pmuv3" for the second PMU? I doubt guessing if these mongoose cores are based on already existing cortex cores is a great idea. >> + compatible = "arm,cortex-a53-pmu"; >> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-affinity = <&cpu0>, >> + <&cpu1>, >> + <&cpu2>, >> + <&cpu3>, >> + <&cpu4>, >> + <&cpu5>, >> + <&cpu6>, >> + <&cpu7>; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + core2 { >> + cpu = <&cpu2>; >> + }; >> + core3 { >> + cpu = <&cpu3>; >> + }; >> + }; >> + >> + cluster1 { >> + core0 { >> + cpu = <&cpu4>; >> + }; >> + core1 { >> + cpu = <&cpu5>; >> + }; >> + core2 { >> + cpu = <&cpu6>; >> + }; >> + core3 { >> + cpu = <&cpu7>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu@100 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x100>; >> + enable-method = "psci"; >> + }; >> + >> + cpu1: cpu@101 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x101>; >> + enable-method = "psci"; >> + }; >> + >> + cpu2: cpu@102 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x102>; >> + enable-method = "psci"; >> + }; >> + >> + cpu3: cpu@103 { >> + device_type = "cpu"; >> + compatible = "arm,cortex-a53"; >> + reg = <0x103>; >> + enable-method = "psci"; >> + }; >> + >> + cpu4: cpu@0 { >> + device_type = "cpu"; >> + compatible = "samsung,mongoose-m2"; >> + reg = <0x0>; >> + enable-method = "psci"; >> + }; >> + >> + cpu5: cpu@1 { >> + device_type = "cpu"; >> + compatible = "samsung,mongoose-m2"; >> + reg = <0x1>; >> + enable-method = "psci"; >> + }; >> + >> + cpu6: cpu@2 { >> + device_type = "cpu"; >> + compatible = "samsung,mongoose-m2"; >> + reg = <0x2>; >> + enable-method = "psci"; >> + }; >> + >> + cpu7: cpu@3 { >> + device_type = "cpu"; >> + compatible = "samsung,mongoose-m2"; >> + reg = <0x3>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + psci { >> + compatible = "arm,psci"; >> + method = "smc"; >> + cpu_suspend = <0xc4000001>; >> + cpu_off = <0x84000002>; >> + cpu_on = <0xc4000003>; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ >> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, >> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; >> + clock-frequency = <26000000>; > Hm? I think this was explicitly disallowed. It's weird. Without the clock-frequency property it fails early during the boot process and I can't get any logs from pstore or simple-framebuffer. Yet it's not set on similar platforms (exynos7885, autov9). Perhaps I could alias the node and set it in the board device tree..? That doesn't sound right. Best regards, Ivaylo >> + }; >> + >> + fixed-rate-clocks { > Keep order of properties, just like DTS coding style asks. > > Anyway, fixed-rate-clocks wrapper is not needed, drop. > >> + oscclk: osc-clock { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + clock-output-names = "oscclk"; >> + }; >> + }; >> + >> + soc: soc@0 { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0x0 0x0 0x0 0x20000000>; >> + >> + chipid@10000000 { >> + compatible = "samsung,exynos8895-chipid", >> + "samsung,exynos850-chipid"; >> + reg = <0x10000000 0x24>; >> + }; >> + >> + gic: interrupt-controller@10200000 { >> + compatible = "arm,gic-400"; >> + #interrupt-cells = <3>; >> + #address-cells = <0>; >> + interrupt-controller; >> + reg = <0x10201000 0x1000>, >> + <0x10202000 0x1000>, >> + <0x10204000 0x2000>, >> + <0x10206000 0x2000>; >> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | >> + IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + >> + pinctrl_alive: pinctrl@164b0000 { >> + compatible = "samsung,exynos8895-pinctrl"; >> + reg = <0x164b0000 0x1000>; >> + >> + wakeup-interrupt-controller { >> + compatible = "samsung,exynos8895-wakeup-eint", >> + "samsung,exynos7-wakeup-eint"; >> + interrupt-parent = <&gic>; >> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; >> + }; >> + }; >> + >> + pinctrl_abox: pinctrl@13e60000 { > This does not look ordered. See DTS coding style. > > Best regards, > Krzysztof >
On Wed, 2024-08-07 at 14:20 +0300, Ivaylo Ivanov wrote: > > On 8/7/24 12:20, Krzysztof Kozlowski wrote: > > On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com wrote: > > > From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> [snip] > > > > > > + > > > + timer { > > > + compatible = "arm,armv8-timer"; > > > + /* Hypervisor Virtual Timer interrupt is not > > > wired to GIC */ > > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) > > > | IRQ_TYPE_LEVEL_LOW)>, > > > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) > > > | IRQ_TYPE_LEVEL_LOW)>, > > > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) > > > | IRQ_TYPE_LEVEL_LOW)>, > > > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) > > > | IRQ_TYPE_LEVEL_LOW)>; > > > + clock-frequency = <26000000>; > > Hm? I think this was explicitly disallowed. > > It's weird. Without the clock-frequency property it fails early > during the > > boot process and I can't get any logs from pstore or simple- > framebuffer. > > Yet it's not set on similar platforms (exynos7885, autov9). Perhaps I > > could alias the node and set it in the board device tree..? That > doesn't > > sound right. This sounds like CNTFRQ_EL0 is not set properly by the firmware. Now, if I read the documentation properly, this can be only set from EL3, which in your case is... not easy. On my Galaxy A8 2018 (Exynos7885) I remember the old Android 8 bootloader not being able to boot mainline, but Android 9 bootloaders did. I did not take the time to check if it was related to this, but it is my guess. Your best bet is that maybe Samsung decided to fix this on the latest bootloader, and upgrading will fix it. (Though if it's already on an Android 9 based bootloader and it's still broken, my guess is a newer version won't fix it, but who knows) Or... Exynos8895 has a known bootrom vulnerability, you could force the SoC into USB Download mode, and use the exploit to boot into a patched bootloader. This is of course pretty tedious. Your only actually relistic choice is submitting without this line and manually adding it while actually using the phone (or making the chainloaded bootloader/boot wrapper add it). Not optimal, but it is what it is... Best Regards, David
On 07/08/2024 13:20, Ivaylo Ivanov wrote: > > On 8/7/24 12:20, Krzysztof Kozlowski wrote: >> On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com wrote: >>> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>> >>> Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy >>> S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu >>> 15 Plus (m1891). Add minimal support for that SoC, including: >>> >>> - All 8 cores via PSCI >>> - ChipID >>> - Generic ARMV8 Timer >>> - Enumarate all pinctrl nodes >>> >>> Further platform support will be added over time. >>> >>> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>> --- >>> .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ >>> arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ >>> 2 files changed, 1631 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >>> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >>> new file mode 100644 >>> index 000000000..1dcb61e2e >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >>> @@ -0,0 +1,1378 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source >>> + * >>> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> +#include "exynos-pinctrl.h" >>> + >>> +&pinctrl_alive { >>> + gpa0: gpa0 { >> I do not believe this was tested. See maintainer SoC profile for Samsung >> Exynos. >> >> Limited review follows due to lack of testing. >> >> >>> +}; >>> diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi >>> new file mode 100644 >>> index 000000000..3ed381ee5 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi >>> @@ -0,0 +1,253 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Samsung's Exynos 8895 SoC device tree source >>> + * >>> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>> + */ >>> + >>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>> + >>> +/ { >>> + compatible = "samsung,exynos8895"; >>> + #address-cells = <2>; >>> + #size-cells = <1>; >>> + >>> + interrupt-parent = <&gic>; >>> + >>> + aliases { >>> + pinctrl0 = &pinctrl_alive; >>> + pinctrl1 = &pinctrl_abox; >>> + pinctrl2 = &pinctrl_vts; >>> + pinctrl3 = &pinctrl_fsys0; >>> + pinctrl4 = &pinctrl_fsys1; >>> + pinctrl5 = &pinctrl_busc; >>> + pinctrl6 = &pinctrl_peric0; >>> + pinctrl7 = &pinctrl_peric1; >>> + }; >>> + >>> + arm-a53-pmu { >> Are there two pmus? > > Hm. The Downstream kernel has them all under one node with compatible > > 'arm,armv8-pmuv3', same as with Exynos 7885. So it should have two PMUs, > > one for each cluster. > > > Considering the second cluster consists of Samsung's custom Mongoose M2 > > cores, what would be the most adequate thing to do? Keep the first PMU as > > "arm,cortex-a53-pmu" and use the SW model "arm,armv8-pmuv3" for the > > second PMU? I doubt guessing if these mongoose cores are based on already > > existing cortex cores is a great idea. I was just wondering why there is only one and called a53. I am not sure what should be for the second, but rather not a software model. Best regards, Krzysztof
On 07/08/2024 19:29, David Virag wrote: > On Wed, 2024-08-07 at 14:20 +0300, Ivaylo Ivanov wrote: >> >> On 8/7/24 12:20, Krzysztof Kozlowski wrote: >>> On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com wrote: >>>> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > [snip] >>>> >>>> + >>>> + timer { >>>> + compatible = "arm,armv8-timer"; >>>> + /* Hypervisor Virtual Timer interrupt is not >>>> wired to GIC */ >>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) >>>> | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) >>>> | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) >>>> | IRQ_TYPE_LEVEL_LOW)>, >>>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) >>>> | IRQ_TYPE_LEVEL_LOW)>; >>>> + clock-frequency = <26000000>; >>> Hm? I think this was explicitly disallowed. >> >> It's weird. Without the clock-frequency property it fails early >> during the >> >> boot process and I can't get any logs from pstore or simple- >> framebuffer. >> >> Yet it's not set on similar platforms (exynos7885, autov9). Perhaps I >> >> could alias the node and set it in the board device tree..? That >> doesn't >> >> sound right. > > This sounds like CNTFRQ_EL0 is not set properly by the firmware. > Now, if I read the documentation properly, this can be only set from > EL3, which in your case is... not easy. > > On my Galaxy A8 2018 (Exynos7885) I remember the old Android 8 > bootloader not being able to boot mainline, but Android 9 bootloaders > did. I did not take the time to check if it was related to this, but it > is my guess. > > Your best bet is that maybe Samsung decided to fix this on the latest > bootloader, and upgrading will fix it. (Though if it's already on an > Android 9 based bootloader and it's still broken, my guess is a newer > version won't fix it, but who knows) If you can update your device to newer Android and it fixes the issue, then please drop the property. If this does not work, then please add a comment like: /* Non-updatable, broken stock Samsung bootloader does not configure CNTFRQ_EL0 */ Best regards, Krzysztof
On 8/9/24 08:48, Krzysztof Kozlowski wrote: > On 07/08/2024 13:20, Ivaylo Ivanov wrote: >> On 8/7/24 12:20, Krzysztof Kozlowski wrote: >>> On 07/08/2024 10:28, ivo.ivanov.ivanov1@gmail.com wrote: >>>> From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>>> >>>> Exynos 8895 SoC is an ARMv8 mobile SoC found in the Samsung Galaxy >>>> S8 (dreamlte), S8 Plus (dream2lte), Note 8 (greatlte) and the Meizu >>>> 15 Plus (m1891). Add minimal support for that SoC, including: >>>> >>>> - All 8 cores via PSCI >>>> - ChipID >>>> - Generic ARMV8 Timer >>>> - Enumarate all pinctrl nodes >>>> >>>> Further platform support will be added over time. >>>> >>>> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>>> --- >>>> .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ >>>> arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ >>>> 2 files changed, 1631 insertions(+) >>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >>>> create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi >>>> >>>> diff --git a/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >>>> new file mode 100644 >>>> index 000000000..1dcb61e2e >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi >>>> @@ -0,0 +1,1378 @@ >>>> +// SPDX-License-Identifier: BSD-3-Clause >>>> +/* >>>> + * Samsung's Exynos 8895 SoC pin-mux and pin-config device tree source >>>> + * >>>> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>>> + */ >>>> + >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> +#include "exynos-pinctrl.h" >>>> + >>>> +&pinctrl_alive { >>>> + gpa0: gpa0 { >>> I do not believe this was tested. See maintainer SoC profile for Samsung >>> Exynos. >>> >>> Limited review follows due to lack of testing. >>> >>> >>>> +}; >>>> diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi >>>> new file mode 100644 >>>> index 000000000..3ed381ee5 >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi >>>> @@ -0,0 +1,253 @@ >>>> +// SPDX-License-Identifier: BSD-3-Clause >>>> +/* >>>> + * Samsung's Exynos 8895 SoC device tree source >>>> + * >>>> + * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >>>> + */ >>>> + >>>> +#include <dt-bindings/interrupt-controller/arm-gic.h> >>>> + >>>> +/ { >>>> + compatible = "samsung,exynos8895"; >>>> + #address-cells = <2>; >>>> + #size-cells = <1>; >>>> + >>>> + interrupt-parent = <&gic>; >>>> + >>>> + aliases { >>>> + pinctrl0 = &pinctrl_alive; >>>> + pinctrl1 = &pinctrl_abox; >>>> + pinctrl2 = &pinctrl_vts; >>>> + pinctrl3 = &pinctrl_fsys0; >>>> + pinctrl4 = &pinctrl_fsys1; >>>> + pinctrl5 = &pinctrl_busc; >>>> + pinctrl6 = &pinctrl_peric0; >>>> + pinctrl7 = &pinctrl_peric1; >>>> + }; >>>> + >>>> + arm-a53-pmu { >>> Are there two pmus? >> Hm. The Downstream kernel has them all under one node with compatible >> >> 'arm,armv8-pmuv3', same as with Exynos 7885. So it should have two PMUs, >> >> one for each cluster. >> >> >> Considering the second cluster consists of Samsung's custom Mongoose M2 >> >> cores, what would be the most adequate thing to do? Keep the first PMU as >> >> "arm,cortex-a53-pmu" and use the SW model "arm,armv8-pmuv3" for the >> >> second PMU? I doubt guessing if these mongoose cores are based on already >> >> existing cortex cores is a great idea. > I was just wondering why there is only one and called a53. I am not sure > what should be for the second, but rather not a software model. > > Best regards, > Krzysztof > Well, as far as I can tell there are 3 options: - use an already defined PMU model for another core (ex. A73) - submit another patch to add a custom mongoose-specific PMU model - omit the mongoose cores PMU entirely My guess is that omitting it entirely with a comment that mentions the issue will be good enough, at least for now. Is that OK for the v3? Best regards, Ivaylo
From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Hi folks, This series adds initial SoC support for the Exynos 8895 SoC and also initial board support for Samsung Galaxy S8 phone (SM-G950F), codenamed dreamlte. The Exynos 8895 SoC is also used in S8 Plus (dream2lte), Note 8 (greatlte) and Meizu 15 Plus (m1891). Currently DT is added for the Exynos 8895 SoC and dreamlte, but it should be really easy to adapt for the other devices with the same SoC. The support added in this series consists of: * cpus * pinctrl * gpio * simple-framebuffer * pstore This is enough to reach a minimal initramfs shell using an upstream kernel. More platform support will be added in the future. The preferred way to boot this device is by using a small shim bl called uniLoader [1], which packages the mainline kernel and DT and jumps to the kernel. This is done in order to work around some issues caused by the stock, and non-replacable Samsung S-Boot bootloader. For example, S-Boot leaves the decon trigger control unset, which causes the framebuffer to not refresh. [1] https://github.com/ivoszbg/uniLoader Kind regards, Ivaylo. Ivaylo Ivanov (10): dt-bindings: arm: cpus: Add Samsung Mongoose M2 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos8895 compatible soc: samsung: exynos-chipid: add exynos8895 SoC support dt-bindings: pinctrl: samsung: Add compatible for Exynos8895 SoC pinctrl: samsung: Add exynos8895 SoC pinctrl configuration dt-bindings: pinctrl: samsung: add exynos8895-wakeup-eint compatible dt-bindings: soc: samsung: exynos-pmu: Add exynos8895 compatible arm64: dts: exynos: Add initial support for exynos8895 SoC dt-bindings: arm: samsung: Document dreamlte board binding arm64: dts: exynos: Add initial support for Samsung Galaxy S8 .../devicetree/bindings/arm/cpus.yaml | 1 + .../bindings/arm/samsung/samsung-boards.yaml | 6 + .../hwinfo/samsung,exynos-chipid.yaml | 1 + .../samsung,pinctrl-wakeup-interrupt.yaml | 1 + .../bindings/pinctrl/samsung,pinctrl.yaml | 1 + .../bindings/soc/samsung/exynos-pmu.yaml | 1 + arch/arm64/boot/dts/exynos/Makefile | 1 + .../boot/dts/exynos/exynos8895-dreamlte.dts | 126 ++ .../boot/dts/exynos/exynos8895-pinctrl.dtsi | 1378 +++++++++++++++++ arch/arm64/boot/dts/exynos/exynos8895.dtsi | 253 +++ .../pinctrl/samsung/pinctrl-exynos-arm64.c | 137 ++ drivers/pinctrl/samsung/pinctrl-exynos.h | 10 + drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + drivers/soc/samsung/exynos-chipid.c | 1 + 15 files changed, 1920 insertions(+) create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts create mode 100644 arch/arm64/boot/dts/exynos/exynos8895-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/exynos/exynos8895.dtsi