[v2,0/4] pinctrl: rockchip: fix RK3328 pinmux bits

The pinmux settings for RK3328 is incomplete, correct the pin bank
settings and recalced mux data according to RK3328 TRM[1].

There was a patch[2] in rockchip-linux kernel repo that cover part of
missing mux settings, unfortunatly it never got into upstream kernel
source.

The last patch fixes an issue in rockchip_pmx_set which is general for
all rockchip platforms that might cause unexpected pinmux to be set to
0.

[1]: https://opensource.rock-chips.com/images/9/97/Rockchip_RK3328TRM_V1.1-Part1-20170321.pdf
[2]: https://github.com/rockchip-linux/kernel/commit/d69af8ab6534bb28c1556076f08d2a5ab4935d95

v2:
  - split commits for GPIO2-B pins and GPIO3-B pins each
  - add a missing Fixes as suggested by Heiko
  - add Reviewed-by to last 2 patches

Huang-Huang Bao (4):
  pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins
  pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins
  pinctrl: rockchip: use dedicated pinctrl type for RK3328
  pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set

 drivers/pinctrl/pinctrl-rockchip.c | 68 ++++++++++++++++++++++++++----
 drivers/pinctrl/pinctrl-rockchip.h |  1 +
 2 files changed, 60 insertions(+), 9 deletions(-)


base-commit: 2df0193e62cf887f373995fb8a91068562784adc
--
2.45.2

Am Freitag, 7. Juni 2024, 16:46:19 CEST schrieb Huang-Huang Bao:
> 
> On 6/7/24 20:32, Heiko Stuebner wrote:
> > Am Donnerstag, 6. Juni 2024, 14:57:53 CEST schrieb Huang-Huang Bao:
> >> The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly
> >> specified in RK3328 TRM, however we can get hint from pad name and its
> >> correspinding IOMUX setting for pins in interface descriptions. The
> >> correspinding IOMIX settings for these pins can be found in the same
> >> row next to occurrences of following pad names in RK3328 TRM.
> >>
> >> GPIO3-B1:  IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6
> >> GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6
> >> GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6
> >> GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6
> >> GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6
> >> GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6
> >>
> >> Add pinmux data to rk3328_mux_recalced_data as mux register offset for
> >> these pins does not follow rockchip convention.
> >>
> >> Signed-off-by: Huang-Huang Bao <i@eh5.me>
> > 
> > This matches the information that I found in my TRM, thanks to your
> > detailed explanation.
> > 
> > Though I of course can't say if the TRM is just wrong or the hardware
> > changed after the pads-description was written.
> > 
> > Did you test the usage of these pins on your board?
> > 
> 
> My board(NanoPi R2S) is kinda integrated and does not have GPIO3 pins so
> I can't test these pins directly.
> 
>  From DTS for RK3328(arch/arm64/boot/dts/rockchip/rk3328*.dts*), there is
> pinctrl/cif-0/dvp_d2d9_m0 referencing part of GPIO3-B1+ pins(GPIO3-B1 to
> GPIO3-B4) that indeed matches "Table 15-1 TSP interface description"
> which contains hint pad names. And this DTS node exists from
> initial commit to add RK3328 dtsi
> (52e02d377a72 "arm64: dts: rockchip: add core dtsi file for RK3328 SoCs").

thanks for digging up this information, that makes sense and stuff looks
pretty much correct with everything combined.

Heiko