From patchwork Wed May 24 09:17:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawen Wu X-Patchwork-Id: 685492 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A125C7EE2C for ; Wed, 24 May 2023 09:20:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240023AbjEXJUf (ORCPT ); Wed, 24 May 2023 05:20:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240253AbjEXJUe (ORCPT ); Wed, 24 May 2023 05:20:34 -0400 Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D9F8D189; Wed, 24 May 2023 02:20:27 -0700 (PDT) X-QQ-mid: bizesmtp69t1684919940ti2h1kv8 Received: from wxdbg.localdomain.com ( [122.235.247.1]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 24 May 2023 17:18:51 +0800 (CST) X-QQ-SSF: 01400000000000I0Z000000A0000000 X-QQ-FEAT: bhet8yMU7vmd71v/PMD2YjSuMylA1q+Tno5ukFfL2nXroAhPM7kSsCa5rEvfM SUlKDyury4IvhlRu2VCHU/ytM5Fb8pLRdAwxxdIFXwbiAquC8n6OCFoi/GsGjfRzLF6pHDl 3FfM4UR4WZz5dinWYW2uOwWvw1osyfdroAOQHsBFaN2I2CFRfuJVzjnfOrk8p0BWVNN138M 0rjFN00+pkQb/EVkSKRzBoiU7gPfpMghGv0B0BphItHe8IvwxXmdLIgV0m0YVtINoi1QQta r058GIL81+jkiDOFrwvYtS67TNZuA2LD3aCCZGVhsYw5cpBNkfFepirv/mN6QV/0h8MM/T9 qyxU5dMcN8XeEvosePQLMf6smoBqtB+EtGPl3FtXgRPRyIwkMw7Q2kgXj2/fA== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 17831172177474358772 From: Jiawen Wu To: netdev@vger.kernel.org, jarkko.nikula@linux.intel.com, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, jsd@semihalf.com, Jose.Abreu@synopsys.com, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk Cc: linux-i2c@vger.kernel.org, linux-gpio@vger.kernel.org, mengyuanlou@net-swift.com, Jiawen Wu Subject: [PATCH net-next v9 0/9] TXGBE PHYLINK support Date: Wed, 24 May 2023 17:17:13 +0800 Message-Id: <20230524091722.522118-1-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybglogicsvrgz:qybglogicsvrgz5a-1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org mplement I2C, SFP, GPIO and PHYLINK to setup TXGBE link. Because our I2C and PCS are based on Synopsys Designware IP-core, extend the i2c-designware and pcs-xpcs driver to realize our functions. v8 -> v9: - rename swnode property for specific I2C platform device - add ".fast_io = true" for I2C regmap - use raw_spinlock_t for GPIO reg lock and adjust its position - remove redundant txgbe->mdiodev - keep reverse x-mass tree order - other minor style changes v7 -> v8: - use macro defined I2C FIFO depth instead of magic number - fix return code of clock create failure - add spinlock for writing GPIO registers - implement triggering GPIO interrupts for both-edge type - remove the condition that enables interrupts - add mii bus check for PCS device - other minor style changes v6 -> v7: - change swnode property of I2C platform to be boolean - use device_property_present() to match I2C device data v5 -> v6: - fix to set error code if pointer of txgbe is NULL - change "if" to "switch" for *_i2c_dw_xfer_quirk() - rename property for I2C device flag - use regmap to access I2C mem region - use DEFINE_RES_IRQ() - use phylink_mii_c45_pcs_get_state() for DW_XPCS_10GBASER v4 -> v5: - add clock register - delete i2c-dw.h with platform data - introduce property "i2c-dw-flags" to match device flags - get resource from platform info to do ioremap - rename quirk functions in i2c-designware-*.c - fix calling txgbe_phylink_init() v3 -> v4: - modify I2C transfer to be generic implementation - avoid to read DW_IC_COMP_PARAM_1 - remove redundant "if" statement - add specific labels to handle error in txgbe_init_phy(), and remove "if" conditions in txgbe_remove_phy() v2 -> v3: - delete own I2C bus master driver, support it in i2c-designware - delete own PCS functions, remove pma configuration and 1000BASE-X mode - add basic function for 10GBASE-R interface in pcs-xpcs - add helper to get txgbe pointer from netdev v1 -> v2: - add comments to indicate GPIO lines - add I2C write operation support - modify GPIO direction functions - rename functions related to PHY interface - add condition on interface changing to re-config PCS - add to set advertise and fix to get status for 1000BASE-X mode - other redundant codes remove Jiawen Wu (9): net: txgbe: Add software nodes to support phylink i2c: designware: Add driver support for Wangxun 10Gb NIC net: txgbe: Register fixed rate clock net: txgbe: Register I2C platform device net: txgbe: Add SFP module identify net: txgbe: Support GPIO to SFP socket net: pcs: Add 10GBASE-R mode for Synopsys Designware XPCS net: txgbe: Implement phylink pcs net: txgbe: Support phylink MAC layer drivers/i2c/busses/i2c-designware-common.c | 8 + drivers/i2c/busses/i2c-designware-core.h | 4 + drivers/i2c/busses/i2c-designware-master.c | 89 ++- drivers/i2c/busses/i2c-designware-platdrv.c | 15 + drivers/net/ethernet/wangxun/Kconfig | 8 + drivers/net/ethernet/wangxun/libwx/wx_lib.c | 3 +- drivers/net/ethernet/wangxun/libwx/wx_type.h | 4 + drivers/net/ethernet/wangxun/txgbe/Makefile | 1 + .../ethernet/wangxun/txgbe/txgbe_ethtool.c | 28 + .../net/ethernet/wangxun/txgbe/txgbe_main.c | 65 +- .../net/ethernet/wangxun/txgbe/txgbe_phy.c | 678 ++++++++++++++++++ .../net/ethernet/wangxun/txgbe/txgbe_phy.h | 10 + .../net/ethernet/wangxun/txgbe/txgbe_type.h | 89 +++ drivers/net/pcs/pcs-xpcs.c | 30 + include/linux/pcs/pcs-xpcs.h | 1 + 15 files changed, 995 insertions(+), 38 deletions(-) create mode 100644 drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c create mode 100644 drivers/net/ethernet/wangxun/txgbe/txgbe_phy.h