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Tue, 14 Mar 2023 15:16:14 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Tue, 14 Mar 2023 15:16:14 -0700 Received: from vdi.nvidia.com (10.127.8.14) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server id 15.2.986.5 via Frontend Transport; Tue, 14 Mar 2023 15:16:13 -0700 From: Asmaa Mnebhi To: , , , , , CC: Asmaa Mnebhi Subject: [PATCH v5 0/2] Support Nvidia BlueField-3 GPIO driver and pin controller Date: Tue, 14 Mar 2023 18:16:07 -0400 Message-ID: <20230314221609.22433-1-asmaa@nvidia.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT076:EE_|CY8PR12MB7585:EE_ X-MS-Office365-Filtering-Correlation-Id: 493e7f26-5247-45b2-ea99-08db24d9bef3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2023 22:16:23.1810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 493e7f26-5247-45b2-ea99-08db24d9bef3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7585 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Support the BlueField-3 SoC GPIO driver for handling interrupts and providing the option to change the direction and value of a GPIO. Support the BlueField-3 SoC pin controller driver for allowing a select number of GPIO pins to be manipulated from userspace or the kernel. The gpio-mlxbf3.c driver handles hardware registers and logic that are different from gpio-mlxbf.c and gpio-mlxbf2.c. For that reason, we have separate drivers for each generation. Changes from v4->v5: gpio-mlxbf3.c: - Update Kconfig dependency in gpio - remove version.h header - use irq_hw_number_t - release lock in mlxbf3_gpio_irq_set_type - add IRQCHIP_IMMUTABLE and GPIOCHIP_IRQ_RESOURCE_HELPERS - remove npins property to use ngpios instead - Assign handle_bad_irq() in probe - Use handle_edge_irq instead pinctrl-mlxbf3.c: - change the driver name to pinctrl-mlxbf3 - alignment cleanup - use PINCTRL_PINFUNCTION - use pinctrl_add_gpio_ranges - use devm_platform_ioremap_resource Asmaa Mnebhi (2): gpio: gpio-mlxbf3: Add gpio driver support pinctrl: pinctrl-mlxbf: Add pinctrl driver support drivers/gpio/Kconfig | 13 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mlxbf3.c | 245 ++++++++++++++++++++++++ drivers/pinctrl/Kconfig | 13 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-mlxbf3.c | 318 +++++++++++++++++++++++++++++++ 6 files changed, 591 insertions(+) create mode 100644 drivers/gpio/gpio-mlxbf3.c create mode 100644 drivers/pinctrl/pinctrl-mlxbf3.c