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Wed, 21 Dec 2022 07:32:48 +0000 Received: from VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::9028:2d9e:dbd:b5c]) by VI1PR0402MB3439.eurprd04.prod.outlook.com ([fe80::9028:2d9e:dbd:b5c%7]) with mapi id 15.20.5924.016; Wed, 21 Dec 2022 07:32:48 +0000 From: Chester Lin To: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Dong Aisheng , Fabio Estevam , Shawn Guo , Jacky Bai , =?utf-8?q?An?= =?utf-8?q?dreas_F=C3=A4rber?= Cc: Chester Lin , s32@nxp.com, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Pengutronix Kernel Team , Larisa Grigore , Ghennadi Procopciuc , Andrei Stefanescu , Radu Pirea , Matthias Brugger Subject: [PATCH v3 0/2] Add pinctrl support for S32 SoC family Date: Wed, 21 Dec 2022 15:32:30 +0800 Message-Id: <20221221073232.21888-1-clin@suse.com> X-Mailer: git-send-email 2.37.3 X-ClientProxiedBy: TYCPR01CA0160.jpnprd01.prod.outlook.com (2603:1096:400:2b1::13) To VI1PR0402MB3439.eurprd04.prod.outlook.com (2603:10a6:803:4::13) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1PR0402MB3439:EE_|DU2PR04MB8917:EE_ X-MS-Office365-Filtering-Correlation-Id: 11a19deb-e6f3-4161-4370-08dae3258f24 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7VM4Xq9OETheHm5JHjKor1QXxrUVI9JCxeP2IstE0ItlUy0iaidmImLf1+4W2gZe4jPep4uW8P6HUovqO9Vmmrzm7DXA5MlXjIjdkjFVcp3qb2D56tCcBBMosXU+EvIERKw3r5i3y7KeVJ5mG+nrLRpw5vkYP8//AAhm6sDRgPjZ4rd4MDHCeRl1G0k5ynsVDuacfgYg2CC6llagzO17j/HnRrQCk2EBKNxaxC+9jvtjkyz5kLWzmhe4kwRgkOP5Wd7RpIZnXT8QwzKxpLdZBynUWqKUZg6NgC7ZTw/IhJW1/1AWRBpSbMoViq/YfkcS+gItwRlVDIdxQej6zBYd9nBZly6/ShR+QqI86xpibOc58F3/0fE4+o+74K8dVDh4pDRZc0Ba0UsUE1C44xNrYR/NKbpPDXhNAfbTdA4lzR1cWFiROv0GnV/GtmTq1Hjn76MjvmvJOqreoobYcqt8bWeJL0cJLZ2iNsz5Svciv9XfttejwivcSvi2in6hcEKSRWEjlUxcwuVQCFp5nnv1GfWHOXZFP8hIZEkKQuSC91j+TCp87fiZTGGBVXjDL7ITtYc71sNTUQzK2jrjJrglUZDLycygJ+T27o/BHY94weCkswodk17Kx++KraNQgJuWAL4hFqAJHzYJMSRMUFOTmmJtZEUkL2yYtGTVgSulY67ZFkOc78yffYN+jdyTcSydYT55h/+VFRSGggZarIO7VjbJZPR53GFhVAKEKBgkp475WVioOOIT2tCASvOjTqgFVeKnwWxJzaEdlXdjq/ffaYfbiqA+LCG3rBL2FcqSOVL1Q2Wgk5nbY+CUTT+8jhntGJtzg7PzRoBk8fN43fcuHi4WYUj+i0YlnUyNgWcumnr4bpVhRptsAmES8o3bUhMoVGE6WE6VI1fI4c9CJA9VyK1hceKJhE1bxRCn5I8R4+ejgFeUFwDwE8c98TKRkyAWCYcI9nUVGnBi9aUoHbQB/iR5Phc9Y4/YXsFfsMLl+fjV6PByHHqDlz7VhArRM7YnrfAScfxP1LzhO1lEKHhoWr0BQghS1v3TQG4q7zTfKCxfD6HQjxn8U3HWlEP8y864MGUNN4ZZkW35Eq/ocGmdrE9gUB4vv/XFUKVap1QKnciAHr64YHm1WmhDadDyXT/GqEa46ZL0Epl2ly9IzRVfFPdhCpRT+6zy/fc//SY47sQ9bTGi6iiZaBJvWBHJ9vqE3RqaIm4Ua6HIS1bBMNC7AE7qaY/QJzlDqCufbzzwBb6FFlAEyGsnt2n2fHxAiCjIvRhrHt8mfmizX+y/JREdTA1gAB5x+4gsVZFxh/jcOwfF7+313GpA6UUJxtkWXSpgyAmk6DQQrrQbH9T2sKrCqKp1MvW8n64JxzNme628oiK/rjs2nZ6Soi+dv5pvjeoWKyVnCOnOkbmvg/ydN2wKeGrXDPZ0jtGrN0fYNifVDHvcrTklM3Wdunc5vV6PhvfLPZToCnIjSnr1xdgYVWUxAUda6xL3AzbSg5mZ7pVtmFcot2Lq55fkwYxUgJXhk7cOVr40PCx4jwd6ag/s0IOyxeeYPADFFGON0a+iN7WJy2M= X-OriginatorOrg: suse.com X-MS-Exchange-CrossTenant-Network-Message-Id: 11a19deb-e6f3-4161-4370-08dae3258f24 X-MS-Exchange-CrossTenant-AuthSource: VI1PR0402MB3439.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Dec 2022 07:32:48.2253 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: f7a17af6-1c5c-4a36-aa8b-f5be247aa4ba X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lnC1vf+BG4Wl7zoFIkwdppDZZWhlTtbRU9TCkvkAE8lXMTh89yPJ9YZDwbetKUO6 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR04MB8917 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hello, Here I want to introduce a new patch series, which aims to support IOMUX functions provided by SIUL2 [System Integration Unit Lite2] on S32 SoCs, such as S32G2. This series is originally from NXP's implementation on CodeAurora[1] and it will be required by upstream kernel for supporting a variety of devices on S32 SoCs which need to config PINMUXs, such as PHYs and MAC controllers. Thanks, Chester Changes in v3: - dt-bindings: - Remove the minItems from reg because there's no optional item for s32g2. - List supported properties of pinmux-node and pincfg-node and add more descriptions. - Adjust the location of "required:". - Fix descriptions and wordings. - Rename the yaml file to nxp,s32g2-siul2-pinctrl.yaml. - Rename pinctrl-s32g.c to pinctrl-s32g2.c - Adjust Kconfig options [menu-invisible] and names [S32G -> S32G2]. - Add .suppress_bind_attrs - Drop the .remove callback and replace the module_platform_driver() call with builtin_platform_driver() Changes in v2: - Move the "nxp,pins" ID range information from DT to the driver. - dt-bindings: - Fix schema issues. - Add descriptions for reg entries. - Revise the example. - Refine the compatible name from "nxp,s32g-..." to "nxp,s32g2-...". - Fix the copyright format suggested by NXP. [1] https://source.codeaurora.org/external/autobsps32/linux/tree/drivers/pinctrl/freescale?h=bsp34.0-5.10.120-rt Chester Lin (2): dt-bindings: pinctrl: add schema for NXP S32 SoCs pinctrl: add NXP S32 SoC family support .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml | 129 +++ drivers/pinctrl/freescale/Kconfig | 14 + drivers/pinctrl/freescale/Makefile | 2 + drivers/pinctrl/freescale/pinctrl-s32.h | 76 ++ drivers/pinctrl/freescale/pinctrl-s32cc.c | 983 ++++++++++++++++++ drivers/pinctrl/freescale/pinctrl-s32g2.c | 773 ++++++++++++++ 6 files changed, 1977 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml create mode 100644 drivers/pinctrl/freescale/pinctrl-s32.h create mode 100644 drivers/pinctrl/freescale/pinctrl-s32cc.c create mode 100644 drivers/pinctrl/freescale/pinctrl-s32g2.c