From patchwork Fri Nov 4 15:19:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Biju Das X-Patchwork-Id: 621865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C8B7C43219 for ; Fri, 4 Nov 2022 15:19:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232518AbiKDPTr (ORCPT ); Fri, 4 Nov 2022 11:19:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32924 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232517AbiKDPTp (ORCPT ); Fri, 4 Nov 2022 11:19:45 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 448331EC69; Fri, 4 Nov 2022 08:19:42 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.96,137,1665414000"; d="scan'208";a="139000228" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 05 Nov 2022 00:19:41 +0900 Received: from localhost.localdomain (unknown [10.226.93.164]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id D32504006A8E; Sat, 5 Nov 2022 00:19:37 +0900 (JST) From: Biju Das To: Linus Walleij , Rob Herring , Krzysztof Kozlowski Cc: Biju Das , Geert Uytterhoeven , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, Chris Paterson , Prabhakar Mahadev Lad Subject: [PATCH v3 0/2] Add RZ/G2L POEG support Date: Fri, 4 Nov 2022 15:19:33 +0000 Message-Id: <20221104151935.1783791-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The output pins of the general PWM timer (GPT) can be disabled by using the port output enabling function for the GPT (POEG). Specifically, either of the following ways can be used. * Input level detection of the GTETRGA to GTETRGD pins. * Output-disable request from the GPT. * Register setting(ie, by setting POEGGn.SSF to 1) This patch series add support for controlling output disable function using sysfs. For output disable operation, POEG group needs to be linked with GPT. Plan to send a follow up patch with renesas,poeg-group as numeric property in pwm bindings for linking both GPT and POEG devices. v2->v3: * Removed Rb tag from Rob as there are some changes introduced. * Added companion property, so that poeg can link with gpt device * Documented renesas,id, as identifier for POEGG{A,B,C,D}. * Updated the binding example. * Added sysfs documentation for output_disable * PWM_RZG2L_GPT implies ARCH_RZG2L. So removed ARCH_RZG2L dependency * Used dev_get_drvdata to get device data * Replaced sprintf->sysfs_emit in show(). v1->v2: * Updated binding description. * Renamed the file poeg-rzg2l->rzg2l-poeg * Removed the macro POEGG as there is only single register and updated rzg2l_poeg_write() and rzg2l_poeg_read() * Updated error handling in probe() REF->v1: * Modelled as pincontrol as most of its configuration is intended to be static and moved driver files from soc to pincontrol directory. * Updated reg size in dt binding example. * Updated Kconfig REF: https://lore.kernel.org/linux-renesas-soc/20220510151112.16249-1-biju.das.jz@bp.renesas.com/ Biju Das (2): dt-bindings: pinctrl: renesas: Add RZ/G2L POEG binding drivers: pinctrl: renesas: Add RZ/G2L POEG driver support .../ABI/testing/sysfs-platform-rzg2l-poeg | 18 ++ .../bindings/pinctrl/renesas,rzg2l-poeg.yaml | 86 ++++++++++ drivers/pinctrl/renesas/Kconfig | 2 + drivers/pinctrl/renesas/Makefile | 2 + drivers/pinctrl/renesas/poeg/Kconfig | 11 ++ drivers/pinctrl/renesas/poeg/Makefile | 2 + drivers/pinctrl/renesas/poeg/rzg2l-poeg.c | 157 ++++++++++++++++++ 7 files changed, 278 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-rzg2l-poeg create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-poeg.yaml create mode 100644 drivers/pinctrl/renesas/poeg/Kconfig create mode 100644 drivers/pinctrl/renesas/poeg/Makefile create mode 100644 drivers/pinctrl/renesas/poeg/rzg2l-poeg.c