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[v1,0/4] ASPEED sgpio driver enhancement.

Message ID 20210526094609.14068-1-steven_lee@aspeedtech.com
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Series ASPEED sgpio driver enhancement. | expand

Message

Steven Lee May 26, 2021, 9:46 a.m. UTC 
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.

For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed dtsi to support the enhanced sgpio.
- Get the max number of sgpio that SoC supported from dts.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins.

Please help to review.

Thanks,
Steven


Steven Lee (4):
  dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
  ARM: dts: aspeed-g6: Add SGPIO node.
  ARM: dts: aspeed-g5: Modify sgpio node for the enhanced sgpio driver.
  gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support

 .../bindings/gpio/aspeed,sgpio.yaml           |  91 +++++++++
 .../devicetree/bindings/gpio/sgpio-aspeed.txt |  46 -----
 arch/arm/boot/dts/aspeed-g5.dtsi              |   3 +-
 arch/arm/boot/dts/aspeed-g6.dtsi              |  32 +++
 drivers/gpio/gpio-aspeed-sgpio.c              | 193 ++++++++++++------
 5 files changed, 250 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
 delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt

Comments

Andrew Jeffery May 27, 2021, 1:27 a.m. UTC | #1 
Hi Steven,

On Wed, 26 May 2021, at 19:16, Steven Lee wrote:
> AST2600 supports 2 SGPIO master interfaces one with 128 pins another one

> with 80 pins.


Is there any chance the serial GPIO controllers can be explicitly 
listed in the Memory Space Allocation Table of the datasheet? Currently 
they're covered by the entry for "GPIO Controller (Parallel GPIO)" 
which is listed as ranging from 0x1e780000-0x1e7807ff.

Admittedly the details are listed in chapter 41 for the GPIO 
Controller, but it would be handy to not have to dig.

> 

> Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

> ---

>  arch/arm/boot/dts/aspeed-g6.dtsi | 32 ++++++++++++++++++++++++++++++++

>  1 file changed, 32 insertions(+)

> 

> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi

> index f96607b7b4e2..556ce9535c22 100644

> --- a/arch/arm/boot/dts/aspeed-g6.dtsi

> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi

> @@ -377,6 +377,38 @@

>  				#interrupt-cells = <2>;

>  			};

>  

> +			sgpiom0: sgpiom@1e780500 {

> +				#gpio-cells = <2>;

> +				gpio-controller;

> +				compatible = "aspeed,ast2600-sgpiom";

> +				reg = <0x1e780500 0x100>;

> +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

> +				max-ngpios = <128>;


I need to think more about this one.

Andrew
Steven Lee May 27, 2021, 4:01 a.m. UTC | #2 
The 05/27/2021 09:27, Andrew Jeffery wrote:
> Hi Steven,

> 

> On Wed, 26 May 2021, at 19:16, Steven Lee wrote:

> > AST2600 supports 2 SGPIO master interfaces one with 128 pins another one

> > with 80 pins.

> 

> Is there any chance the serial GPIO controllers can be explicitly 

> listed in the Memory Space Allocation Table of the datasheet? Currently 

> they're covered by the entry for "GPIO Controller (Parallel GPIO)" 

> which is listed as ranging from 0x1e780000-0x1e7807ff.

> 


I've forwarded your suggestion to designers.
Per the discussion with designers, they may change the
GPIO controller description of Memory Space Allocation Table to
"GPIO Controller (including Parallel and Serial GPIO)".

> Admittedly the details are listed in chapter 41 for the GPIO 

> Controller, but it would be handy to not have to dig.

> 

> > 

> > Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

> > ---

> >  arch/arm/boot/dts/aspeed-g6.dtsi | 32 ++++++++++++++++++++++++++++++++

> >  1 file changed, 32 insertions(+)

> > 

> > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi

> > index f96607b7b4e2..556ce9535c22 100644

> > --- a/arch/arm/boot/dts/aspeed-g6.dtsi

> > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi

> > @@ -377,6 +377,38 @@

> >  				#interrupt-cells = <2>;

> >  			};

> >  

> > +			sgpiom0: sgpiom@1e780500 {

> > +				#gpio-cells = <2>;

> > +				gpio-controller;

> > +				compatible = "aspeed,ast2600-sgpiom";

> > +				reg = <0x1e780500 0x100>;

> > +				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;

> > +				max-ngpios = <128>;

> 

> I need to think more about this one.

> 

> Andrew