| Message ID | 20201007111145.2306213-1-lars.povlsen@microchip.com |
|---|---|
| Headers | show |
| Series | pinctrl: Adding support for Microchip/Microsemi serial GPIO controller | expand |
Hi Lars, a new version of the patch set arrives while I'm reviewing, haha :D On Wed, Oct 7, 2020 at 1:12 PM Lars Povlsen <lars.povlsen@microchip.com> wrote: > This adds DT bindings for the Microsemi/Microchip SGPIO controller, > bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and > mscc,luton-sgpio. > > Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> (...) > + reg: > + description: | > + The GPIO bank number. "0" is designates the input pin bank, > + "1" the output bank. > + maxItems: 1 Excellent. > + '#gpio-cells': > + const: 3 So I thought you needed three cells exactly because the middle cell would get you the bank. That you now have in reg. So what about using the standard twocell? Yours, Linus Walleij
Linus Walleij writes: > Hi Lars, > > a new version of the patch set arrives while I'm reviewing, haha :D Well, luckily not too much changed per Rob's input. > > On Wed, Oct 7, 2020 at 1:12 PM Lars Povlsen <lars.povlsen@microchip.com> wrote: > >> This adds DT bindings for the Microsemi/Microchip SGPIO controller, >> bindings microchip,sparx5-sgpio, mscc,ocelot-sgpio and >> mscc,luton-sgpio. >> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> > > (...) >> + reg: >> + description: | >> + The GPIO bank number. "0" is designates the input pin bank, >> + "1" the output bank. >> + maxItems: 1 > > Excellent. > >> + '#gpio-cells': >> + const: 3 > > So I thought you needed three cells exactly because the > middle cell would get you the bank. That you now have in > reg. So what about using the standard twocell? I think I answered that in the 'v3 2/3' reply. Basically the pins are addressed with two indices, and there are good reasons to expose these to the GPIO cells, f.ex. hardware documentation cross reference. ---Lars > > Yours, > Linus Walleij
The series add support for the serial GPIO controller used by Microchip Sparx5, as well as (MSCC) ocelot/jaguar2 SoCs. The driver now register two separate banks (per instance), one for input pins (the first) and one for output direction. This eliminates the need for specifying the direction as part of the gpio arguments. The (fixed) direction is thus inherent from the gpio handle. v4 changes (binding comments from Rob): - microchip,sgpio-port-ranges changed to uint32-matrix so tuples can be represented properly. - gpio controller node name changed to "gpio@[0-1]" - whitespace fixes - DT files updated as per schema changes v3 changes: - Renamed all usage of "mchp" abbrevation with "microchip". - Split the in/output directions into (two) separate banks. - Eliminated the bindings include file (from above) - Changed SPDX license to "GPL-2.0-or-later" - Change -ENOTSUPP to -EOPNOTSUPP - Minor type/symbol naming changes v2 changes: - Adds both in and output modes. - Use direct adressing of the individual banks (#gpio-cells = <4>), also osoleting need for addressing macros in bindings include file. - Property 'microchip,sgpio-ports' (uint32, bitmask) replaced by proper range set (array of [start,end]) 'microchip,sgpio-port-ranges'. - Fixes whitespace issues in Kconfig file Lars Povlsen (3): dt-bindings: pinctrl: Add bindings for pinctrl-mchp-sgpio driver pinctrl: pinctrl-mchp-sgpio: Add pinctrl driver for Microsemi Serial GPIO arm64: dts: sparx5: Add SGPIO devices .../pinctrl/microchip,sparx5-sgpio.yaml | 140 ++++ MAINTAINERS | 1 + arch/arm64/boot/dts/microchip/sparx5.dtsi | 91 +++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 + .../dts/microchip/sparx5_pcb134_board.dtsi | 258 +++++++ .../dts/microchip/sparx5_pcb135_board.dtsi | 55 ++ drivers/pinctrl/Kconfig | 18 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-microchip-sgpio.c | 676 ++++++++++++++++++ 9 files changed, 1245 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,sparx5-sgpio.yaml create mode 100644 drivers/pinctrl/pinctrl-microchip-sgpio.c -- 2.25.1