| Message ID | 20220712111223.13080-2-rex-bc.chen@mediatek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/mediatek: Add MT8195 DisplayPort driver | expand |
Hi, Bo-Chen: On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This controller is present on several mediatek hardware. Currently > mt8195 and mt8395 have this controller without a functional > difference, > so only one compatible field is added. > > The controller can have two forms, as a normal display port and as an > embedded display port. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dp.yaml | 115 > ++++++++++++++++++ > 1 file changed, 115 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > new file mode 100644 > index 000000000000..e2d6cb314297 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Display Port Controller > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Jitao shi <jitao.shi@mediatek.com> > + > +description: | > + Device tree bindings for the MediaTek display port TX (DP) and > + embedded display port TX (eDP) controller present on some MediaTek > SoCs. > + MediaTek DP and eDP are different hardwares and they have > different > + base address for registers, so we need two different compatibles > to > + separate them. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-dp-tx > + - mediatek,mt8195-edp-tx > + > + reg: > + maxItems: 1 > + > + nvmem-cells: > + maxItems: 1 > + description: efuse data for display port calibration > + > + nvmem-cell-names: > + const: dp_calibration_data > + > + power-domains: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input endpoint of the controller, usually > dp_intf > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: Output endpoint of the controller > + properties: > + endpoint: > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + properties: > + data-lanes: > + description: | > + number of lanes supported by the hardware. > + The possible values: > + 0 - For 1 lane enabled in IP. > + 0 1 - For 2 lanes enabled in IP. > + 0 1 2 3 - For 4 lanes enabled in IP. > + minItems: 1 > + maxItems: 4 > + required: > + - data-lanes > + > + required: > + - port@0 > + - port@1 > + > + max-linkrate-mhz: > + enum: [ 1620, 2700, 5400, 8100 ] > + description: maximum link rate supported by the hardware. > + > +required: > + - compatible > + - reg > + - interrupts > + - ports > + - max-linkrate-mhz > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/mt8195-power.h> > + dp_tx@1c600000 { > + compatible = "mediatek,mt8195-dp-tx"; > + reg = <0x1c600000 0x8000>; > + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; > + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; > + max-linkrate-mhz = <8100>; Why dp-tx has no clock property? I think this device should work with a clock. Regards, CK > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dptx_in: endpoint { > + remote-endpoint = <&dp_intf0_out>; > + }; > + }; > + port@1 { > + reg = <1>; > + dptx_out: endpoint { > + data-lanes = <0 1 2 3>; > + }; > + }; > + }; > + };
On Tue, Jul 12, 2022 at 07:12:14PM +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This controller is present on several mediatek hardware. Currently > mt8195 and mt8395 have this controller without a functional difference, > so only one compatible field is added. > > The controller can have two forms, as a normal display port and as an > embedded display port. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../display/mediatek/mediatek,dp.yaml | 115 ++++++++++++++++++ > 1 file changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > new file mode 100644 > index 000000000000..e2d6cb314297 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > @@ -0,0 +1,115 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Display Port Controller > + > +maintainers: > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > + - Jitao shi <jitao.shi@mediatek.com> > + > +description: | > + Device tree bindings for the MediaTek display port TX (DP) and > + embedded display port TX (eDP) controller present on some MediaTek SoCs. > + MediaTek DP and eDP are different hardwares and they have different > + base address for registers, so we need two different compatibles to > + separate them. As I said before, 'different base address for registers' is not a reason for different compatibles. If it was, then we'd never have a compatible string appear more than once in a DT. Explain WHAT is different within the block. For example[1]. Rob [1] https://lore.kernel.org/all/20220710084133.30976-10-dmitry.baryshkov@linaro.org/ > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-dp-tx > + - mediatek,mt8195-edp-tx > + > + reg: > + maxItems: 1 > + > + nvmem-cells: > + maxItems: 1 > + description: efuse data for display port calibration > + > + nvmem-cell-names: > + const: dp_calibration_data > + > + power-domains: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Input endpoint of the controller, usually dp_intf > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: Output endpoint of the controller > + properties: > + endpoint: > + $ref: /schemas/media/video-interfaces.yaml# > + unevaluatedProperties: false > + properties: > + data-lanes: > + description: | > + number of lanes supported by the hardware. > + The possible values: > + 0 - For 1 lane enabled in IP. > + 0 1 - For 2 lanes enabled in IP. > + 0 1 2 3 - For 4 lanes enabled in IP. > + minItems: 1 > + maxItems: 4 > + required: > + - data-lanes > + > + required: > + - port@0 > + - port@1 > + > + max-linkrate-mhz: > + enum: [ 1620, 2700, 5400, 8100 ] > + description: maximum link rate supported by the hardware. > + > +required: > + - compatible > + - reg > + - interrupts > + - ports > + - max-linkrate-mhz > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/mt8195-power.h> > + dp_tx@1c600000 { > + compatible = "mediatek,mt8195-dp-tx"; > + reg = <0x1c600000 0x8000>; > + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; > + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; > + max-linkrate-mhz = <8100>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dptx_in: endpoint { > + remote-endpoint = <&dp_intf0_out>; > + }; > + }; > + port@1 { > + reg = <1>; > + dptx_out: endpoint { > + data-lanes = <0 1 2 3>; > + }; > + }; > + }; > + }; > -- > 2.18.0 > >
On Wed, 2022-07-13 at 15:56 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This controller is present on several mediatek hardware. Currently > > mt8195 and mt8395 have this controller without a functional > > difference, > > so only one compatible field is added. > > > > The controller can have two forms, as a normal display port and as > > an > > embedded display port. > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > .../display/mediatek/mediatek,dp.yaml | 115 > > ++++++++++++++++++ > > 1 file changed, 115 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > new file mode 100644 > > index 000000000000..e2d6cb314297 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > ml > > @@ -0,0 +1,115 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Display Port Controller > > + > > +maintainers: > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > + - Jitao shi <jitao.shi@mediatek.com> > > + > > +description: | > > + Device tree bindings for the MediaTek display port TX (DP) and > > + embedded display port TX (eDP) controller present on some > > MediaTek > > SoCs. > > + MediaTek DP and eDP are different hardwares and they have > > different > > + base address for registers, so we need two different compatibles > > to > > + separate them. > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt8195-dp-tx > > + - mediatek,mt8195-edp-tx > > + > > + reg: > > + maxItems: 1 > > + > > + nvmem-cells: > > + maxItems: 1 > > + description: efuse data for display port calibration > > + > > + nvmem-cell-names: > > + const: dp_calibration_data > > + > > + power-domains: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + ports: > > + $ref: /schemas/graph.yaml#/properties/ports > > + properties: > > + port@0: > > + $ref: /schemas/graph.yaml#/properties/port > > + description: Input endpoint of the controller, usually > > dp_intf > > + > > + port@1: > > + $ref: /schemas/graph.yaml#/$defs/port-base > > + unevaluatedProperties: false > > + description: Output endpoint of the controller > > + properties: > > + endpoint: > > + $ref: /schemas/media/video-interfaces.yaml# > > + unevaluatedProperties: false > > + properties: > > + data-lanes: > > + description: | > > + number of lanes supported by the hardware. > > + The possible values: > > + 0 - For 1 lane enabled in IP. > > + 0 1 - For 2 lanes enabled in IP. > > + 0 1 2 3 - For 4 lanes enabled in IP. > > + minItems: 1 > > + maxItems: 4 > > + required: > > + - data-lanes > > + > > + required: > > + - port@0 > > + - port@1 > > + > > + max-linkrate-mhz: > > + enum: [ 1620, 2700, 5400, 8100 ] > > + description: maximum link rate supported by the hardware. > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + - ports > > + - max-linkrate-mhz > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/power/mt8195-power.h> > > + dp_tx@1c600000 { > > + compatible = "mediatek,mt8195-dp-tx"; > > + reg = <0x1c600000 0x8000>; > > + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; > > + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; > > + max-linkrate-mhz = <8100>; > > Why dp-tx has no clock property? I think this device should work with > a > clock. > > Regards, > CK > Hello CK, We just need to enable the power domain of dp. The clock of dp is generated by itself and we are not using the global pll to generate clocks. BRs, Bo-Chen > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@0 { > > + reg = <0>; > > + dptx_in: endpoint { > > + remote-endpoint = <&dp_intf0_out>; > > + }; > > + }; > > + port@1 { > > + reg = <1>; > > + dptx_out: endpoint { > > + data-lanes = <0 1 2 3>; > > + }; > > + }; > > + }; > > + }; > >
On Tue, 2022-07-26 at 14:18 +0800, Rex-BC Chen wrote: > On Wed, 2022-07-13 at 15:56 +0800, CK Hu wrote: > > Hi, Bo-Chen: > > > > On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote: > > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > > > This controller is present on several mediatek hardware. > > > Currently > > > mt8195 and mt8395 have this controller without a functional > > > difference, > > > so only one compatible field is added. > > > > > > The controller can have two forms, as a normal display port and > > > as > > > an > > > embedded display port. > > > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > > --- > > > .../display/mediatek/mediatek,dp.yaml | 115 > > > ++++++++++++++++++ > > > 1 file changed, 115 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/mediatek/mediatek,dp.ya > > > ml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp. > > > ya > > > ml > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp. > > > ya > > > ml > > > new file mode 100644 > > > index 000000000000..e2d6cb314297 > > > --- /dev/null > > > +++ > > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp. > > > ya > > > ml > > > @@ -0,0 +1,115 @@ > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: > > > http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: MediaTek Display Port Controller > > > + > > > +maintainers: > > > + - Chun-Kuang Hu <chunkuang.hu@kernel.org> > > > + - Jitao shi <jitao.shi@mediatek.com> > > > + > > > +description: | > > > + Device tree bindings for the MediaTek display port TX (DP) and > > > + embedded display port TX (eDP) controller present on some > > > MediaTek > > > SoCs. > > > + MediaTek DP and eDP are different hardwares and they have > > > different > > > + base address for registers, so we need two different > > > compatibles > > > to > > > + separate them. > > > + > > > +properties: > > > + compatible: > > > + enum: > > > + - mediatek,mt8195-dp-tx > > > + - mediatek,mt8195-edp-tx > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + nvmem-cells: > > > + maxItems: 1 > > > + description: efuse data for display port calibration > > > + > > > + nvmem-cell-names: > > > + const: dp_calibration_data > > > + > > > + power-domains: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: Input endpoint of the controller, usually > > > dp_intf > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/$defs/port-base > > > + unevaluatedProperties: false > > > + description: Output endpoint of the controller > > > + properties: > > > + endpoint: > > > + $ref: /schemas/media/video-interfaces.yaml# > > > + unevaluatedProperties: false > > > + properties: > > > + data-lanes: > > > + description: | > > > + number of lanes supported by the hardware. > > > + The possible values: > > > + 0 - For 1 lane enabled in IP. > > > + 0 1 - For 2 lanes enabled in IP. > > > + 0 1 2 3 - For 4 lanes enabled in IP. > > > + minItems: 1 > > > + maxItems: 4 > > > + required: > > > + - data-lanes > > > + > > > + required: > > > + - port@0 > > > + - port@1 > > > + > > > + max-linkrate-mhz: > > > + enum: [ 1620, 2700, 5400, 8100 ] > > > + description: maximum link rate supported by the hardware. > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - ports > > > + - max-linkrate-mhz > > > + > > > +additionalProperties: false > > > + > > > +examples: > > > + - | > > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > > + #include <dt-bindings/power/mt8195-power.h> > > > + dp_tx@1c600000 { > > > + compatible = "mediatek,mt8195-dp-tx"; > > > + reg = <0x1c600000 0x8000>; > > > + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; > > > + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; > > > + max-linkrate-mhz = <8100>; > > > > Why dp-tx has no clock property? I think this device should work > > with > > a > > clock. > > > > Regards, > > CK > > > > Hello CK, > > We just need to enable the power domain of dp. > The clock of dp is generated by itself and we are not using the > global > pll to generate clocks. Add this to description because this is not trivial. Regards, CK > > BRs, > Bo-Chen > > > > + > > > + ports { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + port@0 { > > > + reg = <0>; > > > + dptx_in: endpoint { > > > + remote-endpoint = <&dp_intf0_out>; > > > + }; > > > + }; > > > + port@1 { > > > + reg = <1>; > > > + dptx_out: endpoint { > > > + data-lanes = <0 1 2 3>; > > > + }; > > > + }; > > > + }; > > > + }; > > > > > >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml new file mode 100644 index 000000000000..e2d6cb314297 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Port Controller + +maintainers: + - Chun-Kuang Hu <chunkuang.hu@kernel.org> + - Jitao shi <jitao.shi@mediatek.com> + +description: | + Device tree bindings for the MediaTek display port TX (DP) and + embedded display port TX (eDP) controller present on some MediaTek SoCs. + MediaTek DP and eDP are different hardwares and they have different + base address for registers, so we need two different compatibles to + separate them. + +properties: + compatible: + enum: + - mediatek,mt8195-dp-tx + - mediatek,mt8195-edp-tx + + reg: + maxItems: 1 + + nvmem-cells: + maxItems: 1 + description: efuse data for display port calibration + + nvmem-cell-names: + const: dp_calibration_data + + power-domains: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input endpoint of the controller, usually dp_intf + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: Output endpoint of the controller + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + properties: + data-lanes: + description: | + number of lanes supported by the hardware. + The possible values: + 0 - For 1 lane enabled in IP. + 0 1 - For 2 lanes enabled in IP. + 0 1 2 3 - For 4 lanes enabled in IP. + minItems: 1 + maxItems: 4 + required: + - data-lanes + + required: + - port@0 + - port@1 + + max-linkrate-mhz: + enum: [ 1620, 2700, 5400, 8100 ] + description: maximum link rate supported by the hardware. + +required: + - compatible + - reg + - interrupts + - ports + - max-linkrate-mhz + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/mt8195-power.h> + dp_tx@1c600000 { + compatible = "mediatek,mt8195-dp-tx"; + reg = <0x1c600000 0x8000>; + power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; + interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; + max-linkrate-mhz = <8100>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; + };