new file mode 100644
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (c) 2022 MediaTek
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/mediatek,dp-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Display Port PHY binding
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+
+description: |
+ Device tree bindings for the Mediatek (embedded) Display Port PHY
+ present on some Mediatek SoCs.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8195-dp-phy
+
+ regmap:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: Phandle to the Display Port node.
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - regmap
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ dp_phy: dp_phy {
+ compatible = "mediatek,mt8195-dp-phy";
+ regmap = <&dp_tx>;
+ #phy-cells = <0>;
+ };
This phy controller is embedded in the Display Port Controller on mt8195 SoCs. Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> --- .../bindings/phy/mediatek,dp-phy.yaml | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dp-phy.yaml