From patchwork Thu Feb 4 14:04:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 61179 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp475699lbl; Thu, 4 Feb 2016 06:04:59 -0800 (PST) X-Received: by 10.66.194.230 with SMTP id hz6mr11023830pac.70.1454594698920; Thu, 04 Feb 2016 06:04:58 -0800 (PST) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c64si1765976pfd.70.2016.02.04.06.04.58; Thu, 04 Feb 2016 06:04:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-fbdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-fbdev-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-fbdev-owner@vger.kernel.org; dkim=neutral (body hash did not verify) header.i=@linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757085AbcBDOE6 (ORCPT + 2 others); Thu, 4 Feb 2016 09:04:58 -0500 Received: from mail-lf0-f53.google.com ([209.85.215.53]:33614 "EHLO mail-lf0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756184AbcBDOE5 (ORCPT ); Thu, 4 Feb 2016 09:04:57 -0500 Received: by mail-lf0-f53.google.com with SMTP id m1so37357762lfg.0 for ; Thu, 04 Feb 2016 06:04:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wbMO9kSRrrLIiKD2+SK/SBgC3KwlhXkR8mC2JUPHgWk=; b=AYIvVwnj0HJXlCcuK5zQKLX8AU4I7975NKrB142NW+Gdml347SomL0sZwcg4f9OpAk Kd/TQgvhw+RvdjENGf+LuZsYBVMuEFxaeNgeytvLmhAfUubhPhDcHvsfU/Rq06RbgiZZ VtJDrtcRjgAmSb84F7FPYSXaysbIsiOCnyp7A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wbMO9kSRrrLIiKD2+SK/SBgC3KwlhXkR8mC2JUPHgWk=; b=K3Mj978Uu/h2x3GtqwIPlz2r8LU43wYweSheTRWTQVVDWuez+4je2/ZzlziNJy3wfl n/irEmvIqnqhChnD4hPk9PKQxlR+fucx+7Jjjk6+JAdtBk9RDk7sMN1eFPT72cYpV3eL lkncrZAoATiDyaMIBHaKl9hYZeeDiO3ofTpA4mjsmrG3S3G4FIBPCh8IuSJ3QTgq7sGO mX/myaQ9xZ/w2ivviD/hzqqLmt5H4hOVMLdinO7tkVR3KWr1iOrdY9Xp9CdR1gDF+j4x bC92P/j60DYFbO2wWvLP31qhBTSDmYASgu9pdfmxI43Z9E6pZSGyC9AcHIygIhSd8i4Q RZLg== X-Gm-Message-State: AG10YOSx5fwMCbE5SExWV4hPlUIycqK/L3j1muDsx2BSZ3Y/XjR0anCfWTwWNn0CgCYF4MDp X-Received: by 10.25.25.142 with SMTP id 136mr3588306lfz.42.1454594695834; Thu, 04 Feb 2016 06:04:55 -0800 (PST) Received: from localhost.localdomain ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id m21sm1576066lfe.29.2016.02.04.06.04.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 04 Feb 2016 06:04:55 -0800 (PST) From: Linus Walleij To: linux-fbdev@vger.kernel.org, Tomi Valkeinen , Jean-Christophe Plagniol-Villard , Pawel Moll , Rob Herring , Russell King Cc: linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Linus Walleij Subject: [PATCH 02/11] video: ARM CLCD: support DT signal inversion flags Date: Thu, 4 Feb 2016 15:04:11 +0100 Message-Id: <1454594660-7532-3-git-send-email-linus.walleij@linaro.org> X-Mailer: git-send-email 2.4.3 In-Reply-To: <1454594660-7532-1-git-send-email-linus.walleij@linaro.org> References: <1454594660-7532-1-git-send-email-linus.walleij@linaro.org> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org The device tree bindings from display-timing.txt allows us to specify if data enable, hsync, vsync or the pixed clock should be inverted on the way to the display. The driver does not currently handle this so add support for those flags as it is needed for the Versatile Sanyo LCD display. Note that the previous behaviour was to invert the pixel clock for all displays, so unless the pixel clock polarity is explicitly defined in the device tree (i.e. the timings node has the "pixelclk-active" property) we fall back to inverting the pixel clock. This needs some extra compatibility code. Since the timing flags have to be set up inside the struct clcd_panel, we need to refactor the code a bit to pass around the panel rather than just the mode. Cc: Pawel Moll Cc: Rob Herring Cc: Russell King Signed-off-by: Linus Walleij --- drivers/video/fbdev/amba-clcd.c | 41 ++++++++++++++++++++++++++++++++++------- 1 file changed, 34 insertions(+), 7 deletions(-) -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-fbdev" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/video/fbdev/amba-clcd.c b/drivers/video/fbdev/amba-clcd.c index c5d1e9ca81ab..8903a42c4122 100644 --- a/drivers/video/fbdev/amba-clcd.c +++ b/drivers/video/fbdev/amba-clcd.c @@ -567,10 +567,11 @@ static int clcdfb_register(struct clcd_fb *fb) #ifdef CONFIG_OF static int clcdfb_of_get_dpi_panel_mode(struct device_node *node, - struct fb_videomode *mode) + struct clcd_panel *clcd_panel) { int err; struct display_timing timing; + struct device_node *timnp; struct videomode video; err = of_get_display_timing(node, "panel-timing", &timing); @@ -579,10 +580,34 @@ static int clcdfb_of_get_dpi_panel_mode(struct device_node *node, videomode_from_timing(&timing, &video); - err = fb_videomode_from_videomode(&video, mode); + err = fb_videomode_from_videomode(&video, &clcd_panel->mode); if (err) return err; + /* Set up some inversion flags */ + timnp = of_get_child_by_name(node, "panel-timing"); + if (timnp && of_property_read_bool(timnp, "pixelclk-active")) { + if (timing.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + clcd_panel->tim2 |= TIM2_IPC; + } else { + /* + * To preserve backwards compatibility, the IPC (inverted + * pixel clock) flag needs to be set on any display that + * doesn't explicitly specify that the pixel clock is + * active on the negative edge. + */ + clcd_panel->tim2 |= TIM2_IPC; + } + + if (timing.flags & DISPLAY_FLAGS_HSYNC_LOW) + clcd_panel->tim2 |= TIM2_IHS; + + if (timing.flags & DISPLAY_FLAGS_VSYNC_LOW) + clcd_panel->tim2 |= TIM2_IVS; + + if (timing.flags & DISPLAY_FLAGS_DE_LOW) + clcd_panel->tim2 |= TIM2_IOE; + return 0; } @@ -615,10 +640,11 @@ static int clcdfb_of_get_backlight(struct device_node *endpoint, } static int clcdfb_of_get_mode(struct device *dev, struct device_node *endpoint, - struct fb_videomode *mode) + struct clcd_panel *clcd_panel) { int err; struct device_node *panel; + struct fb_videomode *mode; char *name; int len; @@ -628,11 +654,12 @@ static int clcdfb_of_get_mode(struct device *dev, struct device_node *endpoint, /* Only directly connected DPI panels supported for now */ if (of_device_is_compatible(panel, "panel-dpi")) - err = clcdfb_of_get_dpi_panel_mode(panel, mode); + err = clcdfb_of_get_dpi_panel_mode(panel, clcd_panel); else err = -ENOENT; if (err) return err; + mode = &clcd_panel->mode; len = clcdfb_snprintf_mode(NULL, 0, mode); name = devm_kzalloc(dev, len + 1, GFP_KERNEL); @@ -663,8 +690,8 @@ static int clcdfb_of_init_tft_panel(struct clcd_fb *fb, u32 r0, u32 g0, u32 b0) }; int i; - /* Bypass pixel clock divider, data output on the falling edge */ - fb->panel->tim2 = TIM2_BCD | TIM2_IPC; + /* Bypass pixel clock divider */ + fb->panel->tim2 |= TIM2_BCD; /* TFT display, vert. comp. interrupt at the start of the back porch */ fb->panel->cntl |= CNTL_LCDTFT | CNTL_LCDVCOMP(1); @@ -704,7 +731,7 @@ static int clcdfb_of_init_display(struct clcd_fb *fb) if (err) return err; - err = clcdfb_of_get_mode(&fb->dev->dev, endpoint, &fb->panel->mode); + err = clcdfb_of_get_mode(&fb->dev->dev, endpoint, fb->panel); if (err) return err;