From patchwork Tue Feb 6 13:57:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Ilpo_J=C3=A4rvinen?= X-Patchwork-Id: 771043 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.14]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA13313173B; Tue, 6 Feb 2024 13:57:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.14 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707227861; cv=none; b=PCvcAb/SiB6Yife0fKOAWXtdOtLPqYK4UycAzHpgAOj9sb8YQYiIzdg3mKqsreUUrM4dx4Uh4Dk8ZXLeCFA2d47wXqklWgW62ex/Tixh8Zqt61w6ggWlm405r23Qs+tIVvilJ6QO56aLQ6S43J50pHe1v/kfsPOzED2vws4IXgo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707227861; c=relaxed/simple; bh=ra907z3zlnnpibGxKFs9lZMq1UE08Wke5uzxQlZ+qJU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=I6h1kQ5xZMjyOgh63uyCw3PtvD5AGOjsv5YXB0nFtOhS+uwzjzsgwjewiqjMWgbqbM26xM3n5ouftLzRzRelDRGw/YteIPi4Jf9fYVwHUFkwqSrJcNnZeBZQvCOsm3PzG+c76yQeFkplXWEeUVcVPOr2ZKWmHR6XPUoA2GldH88= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LGEj7310; arc=none smtp.client-ip=192.198.163.14 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LGEj7310" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1707227860; x=1738763860; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ra907z3zlnnpibGxKFs9lZMq1UE08Wke5uzxQlZ+qJU=; b=LGEj7310su0vSrUOMyVZwDSD9LjZcI6NHmt5gpTJ1a1cBPnWSoEi/Wdh OLQWarVFp2kNRITwl/2OI8Pd4kDp0gQjOAMfsx401DaOcHHrh5XrCW6A5 U8asce5hsij0InrEfyGQxkW2HOR5v56H9lJaZuDZ61DSXAvZYoAFGQPn2 ZUAxp5Cjq1mdgNTPFI/pL4YFmV5GWDQ9bxMqheQePHTrsrIPScqYYVUE4 Iy3ziVKbi+AP9ihX14j1ZX//F03dyKun8V41CJACrdoz50ZpNDTF5hL3K mSyWooqDbZPJT1XFVGsbMrbxD90W20Ha5Nv2rzGIcVgFLOsf0ZzfHKi8P g==; X-IronPort-AV: E=McAfee;i="6600,9927,10975"; a="905185" X-IronPort-AV: E=Sophos;i="6.05,247,1701158400"; d="scan'208";a="905185" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 05:57:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,247,1701158400"; d="scan'208";a="1008739" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.246.36.139]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 05:57:34 -0800 From: =?utf-8?q?Ilpo_J=C3=A4rvinen?= To: linux-pci@vger.kernel.org, Bjorn Helgaas , Jesse Brandeburg , intel-wired-lan@lists.osuosl.org, Tony Nguyen , Mahesh J Salgaonkar , "Oliver O'Halloran" , linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Cc: Ard Biesheuvel , Borislav Petkov , "David S. Miller" , Eric Dumazet , Jakub Kicinski , linux-edac@vger.kernel.org, linux-efi@vger.kernel.org, netdev@vger.kernel.org, Paolo Abeni , Tony Luck , =?utf-8?q?Ilpo_J=C3=A4rvinen?= Subject: [PATCH 1/4] PCI/AER: Cleanup register variable Date: Tue, 6 Feb 2024 15:57:14 +0200 Message-Id: <20240206135717.8565-2-ilpo.jarvinen@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240206135717.8565-1-ilpo.jarvinen@linux.intel.com> References: <20240206135717.8565-1-ilpo.jarvinen@linux.intel.com> Precedence: bulk X-Mailing-List: linux-efi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use u32 for PCIe Capability register variable and name it aercc (Advanced Error Capabilities and Control register, PCIe r6.1 sec 7.8.4.7) instead of temp. Signed-off-by: Ilpo Järvinen --- drivers/pci/pcie/aer.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 05fc30bb5134..e31e6a9a7773 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1210,7 +1210,7 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) { int type = pci_pcie_type(dev); int aer = dev->aer_cap; - int temp; + u32 aercc; /* Must reset in this function */ info->status = 0; @@ -1241,8 +1241,8 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info) return 0; /* Get First Error Pointer */ - pci_read_config_dword(dev, aer + PCI_ERR_CAP, &temp); - info->first_error = PCI_ERR_CAP_FEP(temp); + pci_read_config_dword(dev, aer + PCI_ERR_CAP, &aercc); + info->first_error = PCI_ERR_CAP_FEP(aercc); if (info->status & AER_LOG_TLP_MASKS) { info->tlp_header_valid = 1;