| Message ID | 20221028200950.67505-3-Smita.KoralahalliChannabasappa@amd.com |
|---|---|
| State | Accepted |
| Commit | 2fb6999dd06f3718dcca2cf9b11ea6c9ea9da833 |
| Headers | show |
| Series | efi/cper, cxl: Decode CXL Protocol Errors CPER | expand |
On Fri, 28 Oct 2022 20:09:50 +0000 Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> wrote: > Print the CXL Error Log field as found in CXL Protocol Error Section. > > The CXL RAS Capability structure will be reused by OS First Handling > and the duplication/appropriate placement will be addressed eventually. > > Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> Hi Smita, Ah. Now I see why stuff wasn't in patch 1 that I expected to be there. LGTM Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > v2: > Printed all fields separately. > Printed cap_control. > Prefix cxl_. > Provided the reference. > --- > drivers/firmware/efi/cper_cxl.c | 27 +++++++++++++++++++++++++++ > include/linux/cxl_err.h | 22 ++++++++++++++++++++++ > 2 files changed, 49 insertions(+) > create mode 100644 include/linux/cxl_err.h > > diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c > index 6c94af234be9..53e435c4f310 100644 > --- a/drivers/firmware/efi/cper_cxl.c > +++ b/drivers/firmware/efi/cper_cxl.c > @@ -9,6 +9,7 @@ > > #include <linux/cper.h> > #include "cper_cxl.h" > +#include <linux/cxl_err.h> > > #define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0) > #define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1) > @@ -16,6 +17,7 @@ > #define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3) > #define PROT_ERR_VALID_CAPABILITY BIT_ULL(4) > #define PROT_ERR_VALID_DVSEC BIT_ULL(5) > +#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6) > > static const char * const prot_err_agent_type_strs[] = { > "Restricted CXL Device", > @@ -149,4 +151,29 @@ void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_e > print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, (prot_err + 1), > prot_err->dvsec_len, 0); > } > + > + if (prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG) { > + size_t size = sizeof(*prot_err) + prot_err->dvsec_len; > + struct cxl_ras_capability_regs *cxl_ras; > + > + pr_info("%s Error log length: 0x%04x\n", pfx, prot_err->err_len); > + > + pr_info("%s CXL Error Log:\n", pfx); > + cxl_ras = (struct cxl_ras_capability_regs *)((long)prot_err + size); > + pr_info("%s cxl_ras_uncor_status: 0x%08x", pfx, > + cxl_ras->uncor_status); > + pr_info("%s cxl_ras_uncor_mask: 0x%08x\n", pfx, > + cxl_ras->uncor_mask); > + pr_info("%s cxl_ras_uncor_severity: 0x%08x\n", pfx, > + cxl_ras->uncor_severity); > + pr_info("%s cxl_ras_cor_status: 0x%08x", pfx, > + cxl_ras->cor_status); > + pr_info("%s cxl_ras_cor_mask: 0x%08x\n", pfx, > + cxl_ras->cor_mask); > + pr_info("%s cap_control: 0x%08x\n", pfx, > + cxl_ras->cap_control); > + pr_info("%s Header Log Registers:\n", pfx); > + print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, cxl_ras->header_log, > + sizeof(cxl_ras->header_log), 0); > + } > } > diff --git a/include/linux/cxl_err.h b/include/linux/cxl_err.h > new file mode 100644 > index 000000000000..629e1bdeda44 > --- /dev/null > +++ b/include/linux/cxl_err.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) 2022 Advanced Micro Devices, Inc. > + * > + * Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> > + */ > + > +#ifndef LINUX_CXL_ERR_H > +#define LINUX_CXL_ERR_H > + > +/* CXL RAS Capability Structure, CXL v3.1 sec 8.2.4.16 */ > +struct cxl_ras_capability_regs { > + u32 uncor_status; > + u32 uncor_mask; > + u32 uncor_severity; > + u32 cor_status; > + u32 cor_mask; > + u32 cap_control; > + u32 header_log[16]; > +}; > + > +#endif //__CXL_ERR_
diff --git a/drivers/firmware/efi/cper_cxl.c b/drivers/firmware/efi/cper_cxl.c index 6c94af234be9..53e435c4f310 100644 --- a/drivers/firmware/efi/cper_cxl.c +++ b/drivers/firmware/efi/cper_cxl.c @@ -9,6 +9,7 @@ #include <linux/cper.h> #include "cper_cxl.h" +#include <linux/cxl_err.h> #define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0) #define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1) @@ -16,6 +17,7 @@ #define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3) #define PROT_ERR_VALID_CAPABILITY BIT_ULL(4) #define PROT_ERR_VALID_DVSEC BIT_ULL(5) +#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6) static const char * const prot_err_agent_type_strs[] = { "Restricted CXL Device", @@ -149,4 +151,29 @@ void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_e print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, (prot_err + 1), prot_err->dvsec_len, 0); } + + if (prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG) { + size_t size = sizeof(*prot_err) + prot_err->dvsec_len; + struct cxl_ras_capability_regs *cxl_ras; + + pr_info("%s Error log length: 0x%04x\n", pfx, prot_err->err_len); + + pr_info("%s CXL Error Log:\n", pfx); + cxl_ras = (struct cxl_ras_capability_regs *)((long)prot_err + size); + pr_info("%s cxl_ras_uncor_status: 0x%08x", pfx, + cxl_ras->uncor_status); + pr_info("%s cxl_ras_uncor_mask: 0x%08x\n", pfx, + cxl_ras->uncor_mask); + pr_info("%s cxl_ras_uncor_severity: 0x%08x\n", pfx, + cxl_ras->uncor_severity); + pr_info("%s cxl_ras_cor_status: 0x%08x", pfx, + cxl_ras->cor_status); + pr_info("%s cxl_ras_cor_mask: 0x%08x\n", pfx, + cxl_ras->cor_mask); + pr_info("%s cap_control: 0x%08x\n", pfx, + cxl_ras->cap_control); + pr_info("%s Header Log Registers:\n", pfx); + print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, cxl_ras->header_log, + sizeof(cxl_ras->header_log), 0); + } } diff --git a/include/linux/cxl_err.h b/include/linux/cxl_err.h new file mode 100644 index 000000000000..629e1bdeda44 --- /dev/null +++ b/include/linux/cxl_err.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Advanced Micro Devices, Inc. + * + * Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> + */ + +#ifndef LINUX_CXL_ERR_H +#define LINUX_CXL_ERR_H + +/* CXL RAS Capability Structure, CXL v3.1 sec 8.2.4.16 */ +struct cxl_ras_capability_regs { + u32 uncor_status; + u32 uncor_mask; + u32 uncor_severity; + u32 cor_status; + u32 cor_mask; + u32 cap_control; + u32 header_log[16]; +}; + +#endif //__CXL_ERR_
Print the CXL Error Log field as found in CXL Protocol Error Section. The CXL RAS Capability structure will be reused by OS First Handling and the duplication/appropriate placement will be addressed eventually. Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com> --- v2: Printed all fields separately. Printed cap_control. Prefix cxl_. Provided the reference. --- drivers/firmware/efi/cper_cxl.c | 27 +++++++++++++++++++++++++++ include/linux/cxl_err.h | 22 ++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 include/linux/cxl_err.h