Message ID | 20211210154332.11526-22-brijesh.singh@amd.com |
---|---|
State | New |
Headers | show
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Peter Anvin" <hpa@zytor.com>, Ard Biesheuvel <ardb@kernel.org>, Paolo Bonzini <pbonzini@redhat.com>, Sean Christopherson <seanjc@google.com>, "Vitaly Kuznetsov" <vkuznets@redhat.com>, Jim Mattson <jmattson@google.com>, "Andy Lutomirski" <luto@kernel.org>, Dave Hansen <dave.hansen@linux.intel.com>, Sergio Lopez <slp@redhat.com>, Peter Gonda <pgonda@google.com>, "Peter Zijlstra" <peterz@infradead.org>, Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>, David Rientjes <rientjes@google.com>, Dov Murik <dovmurik@linux.ibm.com>, Tobin Feldman-Fitzthum <tobin@ibm.com>, Borislav Petkov <bp@alien8.de>, Michael Roth <michael.roth@amd.com>, Vlastimil Babka <vbabka@suse.cz>, "Kirill A . Shutemov" <kirill@shutemov.name>, Andi Kleen <ak@linux.intel.com>, "Dr . David Alan Gilbert" <dgilbert@redhat.com>, <tony.luck@intel.com>, <marcorr@google.com>, <sathyanarayanan.kuppuswamy@linux.intel.com>, Brijesh Singh <brijesh.singh@amd.com> Subject: [PATCH v8 21/40] x86/head: re-enable stack protection for 32/64-bit builds Date: Fri, 10 Dec 2021 09:43:13 -0600 Message-ID: <20211210154332.11526-22-brijesh.singh@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211210154332.11526-1-brijesh.singh@amd.com> References: <20211210154332.11526-1-brijesh.singh@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b6c2e1d2-bbcc-4ac1-9fef-08d9bbf3f04f X-MS-TrafficTypeDiagnostic: BYAPR12MB3269:EE_ X-Microsoft-Antispam-PRVS: <BYAPR12MB3269656E3F69270C551AAB2BE5719@BYAPR12MB3269.namprd12.prod.outlook.com> X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GwmYQxR5CgRI2cW2CzREM4ICCsO3m5d3I+9MuMmEYBNfjT66xlDWo51KoxJGA1c7UbQdH4Me0E2NzTuLInO0cC8BcpWgxhrDRVm/HcLv7RSU4Iyt0qD62bfhoxAUFlyN12HfSCRbJPpYOiYNs3RqeafuvZ1GkEg4AuuxgMKvv3Scqt+tZ13fLtUyy/nMvuMe/Qn+yF3OE0BYqiRdzUwYRMq2y2E6OxNFdtsd/NwQWD+9ciBqjf4lcwtU7h2+DTrkfe7a5UbtYldLdZB1WdMh6cGlipgwqDzdQBijZhx9VIX4HRHCyW9Ux6Gje+eu67N1yycBGRf5qUzHkFUOpxxtH/CXjha7HMlTN5J8wkzxIDk/jnitLGSJBFJLJI1vdKPTLcjlokrgjNlfZjZWaweK6z3DU+cBzLW+vFNyJAvrT4FZ2biDJwm7Yx52pzJEe2Qb+ar9fwif1lGk2NKhJHAH7eX5aOfp4VJgguiR7VPG1vPYOOqQbn7KKOnHkM+acSHCMUwc1vUb8dcSW5nJCwZGzojBf23PlR8/Wwuo3pLExy2C+NXu4m4rpcw8zPf9n8QvSBjfVjz7+inM8J9Yhx/0808/CcLnV/oSyN9t0dMDvt6+feE+em6YvfpehQ7L29W+JO8JAjs03iqlBTuYPdQjd7J6QztH3jh7NZWw8skfWOIlxFZDGMCEIrA9i57EyZvFN2tcnkuxfacEaANuxYzL/JtdXv6gzRutZWXPfjlTHjPMNOr8C5vlLRbwhh2Ht9C/f4qzLt4AjPrKdaQVeCUuFDHWeI+xbpoMUYryaoCnX1mFLfHSUaTcQZwyOJuENFUt X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(46966006)(36840700001)(40470700001)(356005)(81166007)(316002)(44832011)(426003)(336012)(83380400001)(54906003)(6666004)(2906002)(36860700001)(7416002)(110136005)(16526019)(186003)(26005)(70206006)(7406005)(7696005)(82310400004)(508600001)(70586007)(8676002)(86362001)(4326008)(40460700001)(5660300002)(1076003)(36756003)(2616005)(8936002)(47076005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2021 15:44:23.2403 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6c2e1d2-bbcc-4ac1-9fef-08d9bbf3f04f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT042.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3269 Precedence: bulk List-ID: <linux-efi.vger.kernel.org> X-Mailing-List: linux-efi@vger.kernel.org |
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Add AMD Secure Nested Paging (SEV-SNP) Guest Support
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expand
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diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile index 2ff3e600f426..4df8c8f7d2ac 100644 --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -48,7 +48,6 @@ endif # non-deterministic coverage. KCOV_INSTRUMENT := n -CFLAGS_head$(BITS).o += -fno-stack-protector CFLAGS_cc_platform.o += -fno-stack-protector CFLAGS_irq.o := -I $(srctree)/$(src)/../include/asm/trace diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 99de8fd461e8..9f8a7e48aca7 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -65,6 +65,22 @@ SYM_CODE_START_NOALIGN(startup_64) leaq (__end_init_task - FRAME_SIZE)(%rip), %rsp leaq _text(%rip), %rdi + + /* + * initial_gs points to initial fixed_per_cpu struct with storage for + * the stack protector canary. Global pointer fixups are needed at this + * stage, so apply them as is done in fixup_pointer(), and initialize %gs + * such that the canary can be accessed at %gs:40 for subsequent C calls. + */ + movl $MSR_GS_BASE, %ecx + movq initial_gs(%rip), %rax + movq $_text, %rdx + subq %rdx, %rax + addq %rdi, %rax + movq %rax, %rdx + shrq $32, %rdx + wrmsr + pushq %rsi call startup_64_setup_env popq %rsi @@ -146,6 +162,14 @@ SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) * added to the initial pgdir entry that will be programmed into CR3. */ pushq %rsi + /* + * NOTE: %gs at this point is a stale data segment left over from the + * real-mode trampoline, so the default stack protector canary location + * at %gs:40 does not yet coincide with the expected fixed_per_cpu struct + * that contains storage for the stack canary. So take care not to add + * anything to the C functions in this path that would result in stack + * protected C code being generated. + */ call __startup_secondary_64 popq %rsi