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[2.7.60.249]) by smtp.gmail.com with ESMTPSA id g198sm11262997wme.23.2021.12.06.03.00.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 06 Dec 2021 03:00:32 -0800 (PST) From: Alexandre Ghiti To: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Zong Li , Anup Patel , Atish Patra , Christoph Hellwig , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Ard Biesheuvel , Arnd Bergmann , Kees Cook , Guo Ren , Heinrich Schuchardt , Mayuresh Chitale , panqinglin2020@iscas.ac.cn, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-efi@vger.kernel.org, linux-arch@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v3 13/13] riscv: Allow user to downgrade to sv39 when hw supports sv48 if !KASAN Date: Mon, 6 Dec 2021 11:46:57 +0100 Message-Id: <20211206104657.433304-14-alexandre.ghiti@canonical.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20211206104657.433304-1-alexandre.ghiti@canonical.com> References: <20211206104657.433304-1-alexandre.ghiti@canonical.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-efi@vger.kernel.org This is made possible by using the mmu-type property of the cpu node of the device tree. By default, the kernel will boot with 4-level page table if the hw supports it but it can be interesting for the user to select 3-level page table as it is less memory consuming and faster since it requires less memory accesses in case of a TLB miss. This functionality requires that kasan is disabled since calling the fdt functions that are kasan instrumented with the MMU off can't work. Signed-off-by: Alexandre Ghiti --- arch/riscv/mm/init.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c index 28de6ea0a720..299b5a44f902 100644 --- a/arch/riscv/mm/init.c +++ b/arch/riscv/mm/init.c @@ -633,10 +633,38 @@ static void __init disable_pgtable_l4(void) * then read SATP to see if the configuration was taken into account * meaning sv48 is supported. */ -static __init void set_satp_mode(void) +static __init void set_satp_mode(uintptr_t dtb_pa) { u64 identity_satp, hw_satp; uintptr_t set_satp_mode_pmd; +#ifndef CONFIG_KASAN + /* + * The below fdt functions are kasan instrumented, since at this point + * there is no mapping for the kasan shadow memory, this can't be used + * when kasan is enabled otherwise it traps. + */ + int cpus_node; + + /* Check if the user asked for sv39 explicitly in the device tree */ + cpus_node = fdt_path_offset((void *)dtb_pa, "/cpus"); + if (cpus_node >= 0) { + int node; + + fdt_for_each_subnode(node, (void *)dtb_pa, cpus_node) { + const char *mmu_type = fdt_getprop((void *)dtb_pa, node, + "mmu-type", NULL); + if (!mmu_type) + continue; + + if (!strcmp(mmu_type, "riscv,sv39")) { + disable_pgtable_l4(); + return; + } + + break; + } + } +#endif set_satp_mode_pmd = ((unsigned long)set_satp_mode) & PMD_MASK; create_pgd_mapping(early_pg_dir, @@ -838,7 +866,7 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) #endif #if defined(CONFIG_64BIT) && !defined(CONFIG_XIP_KERNEL) - set_satp_mode(); + set_satp_mode(dtb_pa); #endif kernel_map.va_pa_offset = PAGE_OFFSET - kernel_map.phys_addr;