[v4,10/10] riscv: defconfig: enable SOPHGO SoC

Message ID	f7dea860fcb0e69203fba9b084a6fb8d84cdef96.1696433229.git.unicorn_wang@outlook.com
State	New
Headers	show Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF0C414261 for <devicetree@vger.kernel.org>; Wed, 4 Oct 2023 15:44:55 +0000 (UTC) From: Chen Wang <unicornxw@gmail.com> To: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, devicetree@vger.kernel.org, guoren@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh+dt@kernel.org, xiaoguang.xing@sophgo.com, apatel@ventanamicro.com Cc: Chen Wang <unicorn_wang@outlook.com>, Conor Dooley <conor.dooley@microchip.com> Subject: [PATCH v4 10/10] riscv: defconfig: enable SOPHGO SoC Date: Wed, 4 Oct 2023 23:44:46 +0800 Message-Id: <f7dea860fcb0e69203fba9b084a6fb8d84cdef96.1696433229.git.unicorn_wang@outlook.com> In-Reply-To: <cover.1696433229.git.unicorn_wang@outlook.com> References: <cover.1696433229.git.unicorn_wang@outlook.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	Add Milk-V Pioneer RISC-V board support \| expand [v4,00/10] Add Milk-V Pioneer RISC-V board support [v4,03/10] dt-bindings: riscv: add sophgo sg2042 bindings [v4,06/10] dt-bindings: timer: Add Sophgo sg2042 CLINT timer [v4,08/10] riscv: dts: add initial Sophgo SG2042 SoC device tree [v4,10/10] riscv: defconfig: enable SOPHGO SoC

Message ID

f7dea860fcb0e69203fba9b084a6fb8d84cdef96.1696433229.git.unicorn_wang@outlook.com

State

New

Headers

From: Chen Wang <unicornxw@gmail.com>
To: aou@eecs.berkeley.edu,
	chao.wei@sophgo.com,
	conor@kernel.org,
	devicetree@vger.kernel.org,
	guoren@kernel.org,
	jszhang@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	palmer@dabbelt.com,
	paul.walmsley@sifive.com,
	robh+dt@kernel.org,
	xiaoguang.xing@sophgo.com,
	apatel@ventanamicro.com
Cc: Chen Wang <unicorn_wang@outlook.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v4 10/10] riscv: defconfig: enable SOPHGO SoC
Date: Wed,  4 Oct 2023 23:44:46 +0800
Message-Id: 
 <f7dea860fcb0e69203fba9b084a6fb8d84cdef96.1696433229.git.unicorn_wang@outlook.com>
In-Reply-To: <cover.1696433229.git.unicorn_wang@outlook.com>
References: <cover.1696433229.git.unicorn_wang@outlook.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

Add Milk-V Pioneer RISC-V board support | expand

Commit Message

Chen Wang Oct. 4, 2023, 3:44 p.m. UTC

From: Chen Wang <unicorn_wang@outlook.com>

Enable SOPHGO SoC config in defconfig to allow the default
upstream kernel to boot on Milk-V Pioneer board.

Acked-by: Chao Wei <chao.wei@sophgo.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index ab86ec3b9eab..bf737cfa1d2c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -32,6 +32,7 @@  CONFIG_SOC_SIFIVE=y
 CONFIG_SOC_STARFIVE=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SOC_VIRT=y
+CONFIG_ARCH_SOPHGO=y
 CONFIG_SMP=y
 CONFIG_HOTPLUG_CPU=y
 CONFIG_PM=y

[v4,10/10] riscv: defconfig: enable SOPHGO SoC

Commit Message

Patch