From patchwork Tue Jan 9 08:23:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshinori Sato X-Patchwork-Id: 761215 Received: from sakura.ysato.name (ik1-413-38519.vs.sakura.ne.jp [153.127.30.23]) by smtp.subspace.kernel.org (Postfix) with ESMTP id BD5923B7A1; Tue, 9 Jan 2024 08:24:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=users.sourceforge.jp Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=users.sourceforge.jp Received: from SIOS1075.ysato.name (ZM005235.ppp.dion.ne.jp [222.8.5.235]) by sakura.ysato.name (Postfix) with ESMTPSA id BF1121C0CAE; Tue, 9 Jan 2024 17:24:33 +0900 (JST) From: Yoshinori Sato To: linux-sh@vger.kernel.org Cc: Yoshinori Sato , Damien Le Moal , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Thomas Gleixner , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm , Daniel Lezcano , Rich Felker , John Paul Adrian Glaubitz , Lee Jones , Helge Deller , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Yang Xiwen , Sebastian Reichel , Linus Walleij , Randy Dunlap , Arnd Bergmann , Vlastimil Babka , Hyeonggon Yoo <42.hyeyoo@gmail.com>, David Rientjes , Baoquan He , Andrew Morton , Guenter Roeck , Stephen Rothwell , Azeem Shaikh , Javier Martinez Canillas , Max Filippov , Palmer Dabbelt , Bin Meng , Jonathan Corbet , Jacky Huang , Lukas Bulwahn , Biju Das , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Sam Ravnborg , Sergey Shtylyov , Michael Karcher , Laurent Pinchart , linux-ide@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-pci@vger.kernel.org, linux-serial@vger.kernel.org, linux-fbdev@vger.kernel.org Subject: [DO NOT MERGE v6 29/37] sh: SH7751R SoC Internal peripheral definition dtsi. Date: Tue, 9 Jan 2024 17:23:26 +0900 Message-Id: X-Mailer: git-send-email 2.39.2 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 SH7751R internal peripherals device tree. Signed-off-by: Yoshinori Sato --- arch/sh/boot/dts/sh7751r.dtsi | 148 ++++++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) create mode 100644 arch/sh/boot/dts/sh7751r.dtsi diff --git a/arch/sh/boot/dts/sh7751r.dtsi b/arch/sh/boot/dts/sh7751r.dtsi new file mode 100644 index 000000000000..f006f7bacf99 --- /dev/null +++ b/arch/sh/boot/dts/sh7751r.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the SH7751R SoC + */ + +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "renesas,sh4", "renesas,sh2"; + device_type = "cpu"; + reg = <0>; + clocks = <&cpg SH7750_CPG_ICK>; + clock-names = "ick"; + icache-size = <16384>; + icache-line-size = <32>; + dcache-size = <32768>; + dcache-line-size = <32>; + }; + }; + + xtal: oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "xtal"; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&shintc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + cpg: clock-controller@ffc00000 { + #clock-cells = <1>; + #power-domain-cells = <0>; + compatible = "renesas,sh7751r-cpg"; + clocks = <&xtal>; + clock-names = "xtal"; + reg = <0xffc00000 20>, <0xfe0a0000 16>; + reg-names = "FRQCR", "CLKSTP00"; + renesas,mode = <0>; + }; + + shintc: interrupt-controller@ffd00000 { + compatible = "renesas,sh7751-intc"; + #interrupt-cells = <1>; + interrupt-controller; + reg = <0xffd00000 20>, <0xfe080000 128>; + reg-names = "ICR", "INTPRI00"; + renesas,ipr-map = <0x240 IPRD IPR_B12>, /* IRL0 */ + <0x2a0 IPRD IPR_B8>, /* IRL1 */ + <0x300 IPRD IPR_B4>, /* IRL2 */ + <0x360 IPRD IPR_B0>, /* IRL3 */ + <0x400 IPRA IPR_B12>, /* TMU0 */ + <0x420 IPRA IPR_B8>, /* TMU1 */ + <0x440 IPRA IPR_B4>, /* TMU2 TNUI */ + <0x460 IPRA IPR_B4>, /* TMU2 TICPI */ + <0x480 IPRA IPR_B0>, /* RTC ATI */ + <0x4a0 IPRA IPR_B0>, /* RTC PRI */ + <0x4c0 IPRA IPR_B0>, /* RTC CUI */ + <0x4e0 IPRB IPR_B4>, /* SCI ERI */ + <0x500 IPRB IPR_B4>, /* SCI RXI */ + <0x520 IPRB IPR_B4>, /* SCI TXI */ + <0x540 IPRB IPR_B4>, /* SCI TEI */ + <0x560 IPRB IPR_B12>, /* WDT */ + <0x580 IPRB IPR_B8>, /* REF RCMI */ + <0x5a0 IPRB IPR_B4>, /* REF ROVI */ + <0x600 IPRC IPR_B0>, /* H-UDI */ + <0x620 IPRC IPR_B12>, /* GPIO */ + <0x640 IPRC IPR_B8>, /* DMAC DMTE0 */ + <0x660 IPRC IPR_B8>, /* DMAC DMTE1 */ + <0x680 IPRC IPR_B8>, /* DMAC DMTE2 */ + <0x6a0 IPRC IPR_B8>, /* DMAC DMTE3 */ + <0x6c0 IPRC IPR_B8>, /* DMAC DMAE */ + <0x700 IPRC IPR_B4>, /* SCIF ERI */ + <0x720 IPRC IPR_B4>, /* SCIF RXI */ + <0x740 IPRC IPR_B4>, /* SCIF BRI */ + <0x760 IPRC IPR_B4>, /* SCIF TXI */ + <0x780 IPRC IPR_B8>, /* DMAC DMTE4 */ + <0x7a0 IPRC IPR_B8>, /* DMAC DMTE5 */ + <0x7c0 IPRC IPR_B8>, /* DMAC DMTE6 */ + <0x7e0 IPRC IPR_B8>, /* DMAC DMTE7 */ + <0xa00 INTPRI00 IPR_B0>, /* PCIC PCISERR */ + <0xa20 INTPRI00 IPR_B4>, /* PCIC PCIDMA3 */ + <0xa40 INTPRI00 IPR_B4>, /* PCIC PCIDMA2 */ + <0xa60 INTPRI00 IPR_B4>, /* PCIC PCIDMA1 */ + <0xa80 INTPRI00 IPR_B4>, /* PCIC PCIDMA0 */ + <0xaa0 INTPRI00 IPR_B4>, /* PCIC PCIPWON */ + <0xac0 INTPRI00 IPR_B4>, /* PCIC PCIPWDWN */ + <0xae0 INTPRI00 IPR_B4>, /* PCIC PCIERR */ + <0xb00 INTPRI00 IPR_B8>, /* TMU3 */ + <0xb80 INTPRI00 IPR_B12>; /* TMU4 */ + }; + + /* sci0 is rarely used, so it is not defined here. */ + scif1: serial@ffe80000 { + compatible = "renesas,scif-sh7751", "renesas,scif"; + reg = <0xffe80000 0x100>; + interrupts = <0x700>, + <0x720>, + <0x760>, + <0x740>; + interrupt-names = "eri", "rxi", "txi", "bri"; + clocks = <&cpg SH7750_MSTP_SCIF>; + clock-names = "fck"; + power-domains = <&cpg>; + status = "disabled"; + }; + + /* Normally ch0 and ch1 are used, so we will define ch0 to ch2 here. */ + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-sh7750", "renesas,tmu"; + reg = <0xffd80000 12>; + interrupts = <0x400>, + <0x420>, + <0x440>, + <0x460>; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&cpg SH7750_MSTP_TMU012>; + clock-names = "fck"; + power-domains = <&cpg>; + #renesas,channels = <3>; + }; + + pcic: pci@fe200000 { + compatible = "renesas,sh7751-pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 0>; + reg = <0xfe200000 0x0400>, + <0xff800000 0x0100>; + status = "disabled"; + }; + }; +};